Eduard Alarcón

Modeling of Quantization Effects in Digitally Controlled DC–DC Converters

In digitally controlled dc-dc converters with a single voltage feedback loop, the two quantizers, namely the analog-to-digital (A/D) converter and the digital pulse-width modulator (DPWM), can cause undesirable limit-cycle oscillations. In this paper, static and dynamic models that include the quantization effects are derived and used to explain the origins of limit-cycle oscillations. In the static model, existence of dc solution, which is a necessary no-limit-cycle condition, is examined using a graphical method. Based on the generalized describing function method, the amplitude and offset-dependent gain model of a quantizer is applied to derive the dynamic system model. From the static and dynamic models, no-limit-cycle conditions associated with A/D, DPWM and compensator design criteria are derived. The conclusions are illustrated by simulation and experimental examples

Digital pulse width modulator architectures

This paper presents a survey and classification of architectures for integrated circuit implementation of digital pulse-width modulators (DPWM) targeting digital control of high-frequency switching DC-DC power converters. Previously presented designs are identified as particular cases of the proposed classification. In order to optimize circuit resources in terms of occupied area and power consumption, a general architecture based on tapped delay lines is proposed, which includes segmentation of the input digital code to drive binary weighted delay cells and thermometer-decoded unary delay cells. Integrated circuit design of a particular example of the segmented DPWM is described. The segmented DPWM prototype chip operates at 1 MHz switching frequency and has low power consumption and very small silicon area (0.07 mm/sup 2/ in a standard 0.5 micron CMOS process). Experimental results validate the functionality of the proposed segmented DPWM.

Proximate Time-Optimal Digital Control for Synchronous Buck DC–DC Converters

This paper introduces an approach to near time-optimal control for synchronous buck dc-dc converters. The proposed proximate time-optimal digital (PTOD) controller is a combination of a constant-frequency pulsewidth modulation (PWM) controller employing a linear PID compensator close to a reference point, and a linear or nonlinear switching surface controller (SSC) away from the reference, together with smooth transitions between the two. A hybrid capacitor current estimator enables switching surface evaluation and eliminates the need for current sensing. The SSC, which is implemented as a small Verilog HDL module, can be easily added to an existing digital PWM controller to construct the PTOD controller. In steady state, the controller operates exactly the same as a standard constant-frequency PWM controller with a linear PID compensator. Simulation and experimental results are shown for a 6.5 V-to-1.3 V, 10A synchronous buck converter.

Three-level buck converter for envelope tracking applications

This letter proposes a three-level buck converter for tracking applications such as envelope-tracking in radio frequency power amplifiers (RFPAs). It is shown that the three-level buck converter can offer advantages in terms of switching ripples, losses, bandwidth, or the size of magnetic components compared to a standard buck or a two-phase buck converter. Experimental results illustrate improved efficiency and ripple rejection in an RFPA envelope-tracking application representative for low-power battery-operated systems.

Modeling of quantization effects in digitally controlled DC-DC converters

In digitally controlled dc-dc converters with a single voltage feedback loop, the two quantizers, namely the analog-to-digital (A/D) converter and the digital pulse-width modulator (DPWM), can cause undesirable limit-cycle oscillations. In this paper, static and dynamic models that include the quantization effects are derived and used to explain the origins of limit-cycle oscillations. In the static model, existence of dc solution, which is a necessary no-limit-cycle condition, is examined using a graphical method. Based on the generalized describing function method, the amplitude and offset-dependent gain model of a quantizer is applied to derive the dynamic system model. From the static and dynamic models, no-limit-cycle conditions associated with A/D, DPWM and compensator design criteria are derived. The conclusions are illustrated by simulation and experimental examples

Band Separation and Efficiency Optimization in Linear-Assisted Switching Power Amplifiers

Linear-assisted switching power amplifiers are based on combinations of switching converters (for high efficiency) and linear amplifiers (for high-speed, wide bandwidth responses) in applications such as envelope tracking for RF power amplifiers in polar modulation architectures, or audio amplifiers. This paper describes an approach to band separation and filter design to maximize the system efficiency and achieve near-ideal, wide-bandwidth responses. An experimental prototype is described, including a synchronous buck converter in combination with a class-AB linear amplifier. Experimental results for square wave and rectified sinusoid input signals demonstrate high bandwidth and high efficiency of the linear-assisted switching power amplifiers with optimized band separation.

Three-level buck converter for envelope tracking in RF power amplifiers

This paper proposes a three-level buck converter for efficient wide-bandwidth envelope tracking in RF power amplifiers (RFPA). The focus is on low-power battery-operated systems, and the goal is to enable practical implementation of the envelope elimination and restoration (EER) technique, which theoretically allows realization of a highly linear, highly efficient RFPA for non-constant envelope modulations. In terms of ripple, switching frequency and bandwidth tradeoffs, it is shown that the three-level buck converter is similar to the two-phase configuration, while employing a single inductor in the power stage. Additionally, a digital control technique for regulation of the flying capacitor voltage is proposed to ensure signal tracking fidelity. Experimental results show the improved performance of a three-level buck converter prototype as regards efficiency and ripple rejection for the illustrative case of tracking the envelope of a two-tone test signal

Graphene-enabled wireless communication for massive multicore architectures

Current trends in microprocessor architecture design are leading towards a dramatic increase of core-level parallelization, wherein a given number of independent processors or cores are interconnected. Since the main bottleneck is foreseen to migrate from computation to communication, efficient and scalable means of inter-core communication are crucial for guaranteeing steady performance improvements in many-core processors. As the number of cores grows, it remains unclear whether initial proposals, such as the Network-on-Chip (NoC) paradigm, will meet the stringent requirements of this scenario. This position paper presents a new research area where massive multicore architectures have wireless communication capabilities at the core level. This goal is feasible by using graphene-based planar antennas, which can radiate signals at the Terahertz band while utilizing lower chip area than its metallic counterparts. To the best of our knowledge, this is the first work that discusses the utilization of graphene-enabled wireless communication for massive multicore processors. Such wireless systems enable broadcasting, multicasting, all-to-all communication, as well as significantly reduce many of the issues present in massively multicore environments, such as data coherency, consistency, synchronization and communication problems. Several open research challenges are pointed out related to implementation, communications and multicore architectures, which pave the way for future research in this multidisciplinary area.

Survey and Benchmark of Fully Integrated Switching Power Converters: Switched-Capacitor Versus Inductive Approach

This paper surveys and discusses the state-of-the-art of integrated switched-capacitor and inductive power converters. After introducing applications that drive the need for integrated switching power converters, implementation issues to be addressed for integrated switched-capacitor and inductive converters are given, as well as design examples. At the end of this paper, a comprehensive set of integrated power converters are compared in terms of the main specifications and performance metrics, thereby allowing a categorization and providing application-oriented design guidelines.

Application of sliding-mode control to the design of a buck-based sinusoidal generator

This paper is devoted to the design of a sliding-mode control scheme for a buck-based inverter, with programmable amplitude, frequency, and DC offset, with no external sinusoidal reference required. A general procedure for obtaining an autonomous (time independent) switching surface from a time-dependent one is presented. For this surface, the system exhibits a zeroth-order dynamics in sliding motion. On the other hand, from the sliding-domain analysis, a set of design restrictions is established in terms of the inverter output filter Bode diagram and the output signal parameters (amplitude, frequency and DC offset), facilitating the subsequent design procedure. The control scheme is robust with respect to both power-stage parameter variations and external disturbances and can be implemented by means of conventional electronic circuitry. Simulations and experimental results for both reactive and nonlinear loads are presented.