Herminio Martínez

Modeling of linear-assisted DC-DC converters

This paper shows the modeling of a linear-assisted or hybrid (linear & switching) DC-DC converters. In this kind of converters, an auxiliary linear regulator is used, which objective is to cancel the ripple at the output voltage and provide fast responses for load variations. On the other hand, a switching converter, connected in parallel with the linear regulator, allows to supply almost the whole output current demanded by the load. The objective of this topology is to take advantage of the suitable regulation characteristics that series linear voltage regulators have, but almost achieving the high efficiency that switching DC-DC converters provide. Linear-assisted DC-DC converters are feedback systems with potential instability. Therefore, their modeling is mandatory in order to obtain design guidelines and assure stability of the implemented power supply system.

High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator

This paper presents a CMOS low quiescent current output-capacitorless low-dropout regulator (LDO) based on a high slew rate current mode transconductance amplifier (CTA) as error amplifier. Using local common-mode feedback (LCMFB) in the proposed CTA, the order of transfer characteristic of the circuit is increased. Therefore, the slew rate at the gate of pass transistor is enhanced. This improves the LDO load transient characteristic even at low quiescent current. The proposed LDO topology has been designed and post simulated in HSPICE in a 0.18@?m CMOS process to supply the load current between 0 and 100mA. The dropout voltage of the LDO is set to 200mV for 1.2-2V input voltage. Post-layout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10 and 100pF. The total quiescent current of the LDO including the current consumed by the reference buffer circuit is only 3.7@?A. A final benchmark comparison considering all relevant performance metrics is presented.

Fractional DC/DC converter in solar-powered electrical generation systems

This paper deals with the fractional modeling of a DC-DC buck-boost converter, suitable in solar-powered electrical generation systems, and the design of a fractional controller for the aforementioned switching converter. Although the modeling and design of the controller is carried out for this particular DC-DC converter, it can be easily extended to other kind of switching converter. In addition, the comparison between integer-order plant/controller and fractional-order plants/controller is carried out. The article also shows that, under the same design conditions, the fractional-order controller has a better performance and behaviour than the classical integer-order controller in both situations, that is, with integer-order plant and fractional-order plant models.

Linear-assisted DC-DC converter based on CMOS technology

This article shows the design of an on-chip CMOS implementation for an alternative topology to classic switching DC-DC power converters. In the presented technique, an auxiliary linear regulator is used to cancel the output voltage ripple and provides fast responses for load and line variations. On the other hand, a switching converter, connected in parallel, allows supplying almost the whole output current demanded by the load. The objective of this linear-assisted converter or hybrid topology is to achieve a high efficiency of switching converters, with suitable load and line regulation features, typical of linear regulators. In order to implement on-chip power supply systems and on-chip power management systems with low- to-medium current consumption, this structure has good features. In this kind of on-chip applications, CMOS is the current prevailing technology. Thus, the article shows a possible implementation of a linear-assisted converter based on a 0.8-mum CMOS technology.

Active inductor-based tunable impedance matching network for RF power amplifier application

This paper presents the use of a new structure of active inductor named cascoded flipped-active inductor (CASFAI) in a T-type high-pass tunable output matching network of a class-E RF power amplifier (RFPA) to control the output power and enhance the efficiency. The designed CASFAI behaves as an inductor in the frequency range of 0-6.9GHz, and has reached to a maximum quality factor of 4406, inductance value of 7.56nH, 3rd order harmonic distortion better than -30dB for 0dBm input power, while consumes only 2mW power. In order to consider the performance of the proposed active inductor-based tunable output matching network on the output power level and power added efficiency (PAE) of RFPA, the CASFAI is applied as a variable inductor to the output matching network of RFPA. The overall circuit is designed and validated in ADS in a 0.18?m CMOS process and 1.5V supply voltage. The results indicate that by increasing the inductance value of the matching network in constant operating frequency, the PAE peak moves from high power to low power levels without any degradation. Therefore, it is possible to maintain the power efficiency at the same maximum level for lower input drive levels. The use of a new CASFAI in a tunable matching network of a class-E RFPA is presented.The designed CASFAI behaves as an inductor in the frequency range of 0-6.9GHz.It has reached to a maximum quality factor of 4406 and inductance value of 7.56nH.The CASFAI is applied as a variable inductor to the output matching network of RFPA.The overall circuit is validated in a 0.18?m CMOS process and 1.5V supply voltage.

Output-capacitorless CMOS LDO regulator based on high slew-rate current-mode transconductance amplifier

A low quiescent current output-capacitorless CMOS LDO regulator based on a high slew-rate current-mode transconductance amplifier (CTA) as an error amplifier is presented. Load transient characteristic of the proposed LDO is improved even at low quiescent currents, by using a local common-mode feedback (LCMFB) in the proposed CTA. This provides an increase in the order of transfer characteristic of the circuit, thereby enhancing the slew-rate at the gate of pass transistor. The proposed CTA-based LDO topology has been designed and post-layout simulated in HSPICE, in a 0.18 μm CMOS process to supply a load current between 0-100 mA. Postlayout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10-100 pF.

Dynamic analysis of hybrid DC-DC converters

This paper shows the analysis and implementation of a hybrid DC-DC power converter. The proposed topology consists of a series linear voltage regulator in parallel with a switching step-down converter. This topology can provide small ripple at the output voltage, fast responses for load variations and high efficiency for high load current conditions. In the hybrid structures there is not a classical feedback loop as in DC-DC converters, but they are feedback systems too. Therefore, their small- signal analysis is important to assure stability of the implemented power supply system. From the analysis proposed we deduce the critical components that induce instability to the converter and how to improve the final design.

Nonlinear analytical model of the MRC (MOS resistive circuit)

We analyze the significant departures between the predicted behavior and the actual performance of MOS Resistive Circuit cells (MRC) due to mobility degradation. These effects are mainly a difference in the value of the resistance implemented, and a nonlinear behavior. A model including these effects is proposed and shown to work through an example.

Design and implementation of an MRC-C TQE filter with on-chip automatic tuning

This work describes the design and implementation of the tuning loops (both central frequency and quality factor control loops) for a bandpass continuous-time fully-balanced filter based on a modification of the Transimpedance Q-Enhancement (TQE) structure, intended for audio-band applications. The circuit has been designed and fabricated in a CMOS 0.8 /spl mu/m technology, and MRC (MOS Resistive Circuit) cells have been used to implement electronically tunable active resistors. Both post-layout transistor-level simulation results and experimental results validate the functionality of the tuning system.

Output-capacitorless segmented low-dropout voltage regulator with controlled pass transistors

This article presents a low quiescent current output-capacitorless quasi-digital complementary metal-oxide-semiconductor CMOS low-dropout LDO voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade-off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.18µm CMOS process to supply a stable load current between 0 and 100mA with a 40pF on-chip output capacitor, while consuming 4.8µA quiescent current. The dropout voltage of the LDO is set to 200mV for 1.8V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively. Copyright