Gerard Villar

Synchronization of nonlinear electronic oscillators for neural computation

This paper deals with coupled oscillators as the building blocks of a bioinspired computing paradigm and their implementation. In order to accomplish the low-power and fast-processing requirements of autonomous applications, we study the microelectronic analog implementation of physical oscillators, instead of the software computer-simulated implementation. With this aim, the original oscillator has been adapted to a suitable microelectronic form. So as to study the hardware nonlinear oscillators, we propose two macro models, demonstrating that they preserve the synchronization properties. Secondary effects such as mismatch and output delay and their relation to network synchronization are analyzed and discussed. We show the correct operation of the proposed electronic oscillators with simulations and experimental results from a manufactured integrated test circuit. The proposed architecture is intended to perform the scene segmentation stage of an autonomous focal-plane self-contained visual processing system for artificial vision applications.

Monolithic integration of a 3-level DCM-operated low-floating-capacitor buck converter for DC-DC step-down donversion in standard CMOS

This paper addresses the fully monolithic integration of a 3-level 2-phase buck converter for DC-DC step-down conversion in standard CMOS. First it is shown a design-oriented analysis of the converter considering DCM mode (due to PFM operation for low output currents) and with low values of the floating capacitor (to improve integrability). At transistor-level, a self-driving scheme is proposed which allows supplying the tapered buffer drivers from the floating capacitor, thereby reducing the voltage across the power MOSFETs gate dielectric and improving efficiency. The presented converter exhibits enhanced degrees of freedom in the design space defined by the switching frequency, inductor and capacitors values, which have an impact on the achievable efficiency, occupied silicon area and output ripple. An optimized design exploration is carried out for V bat = 3.6 V, Vo = 1 V, Io = 100 mA, DeltaVo = 50 mV, which yields a converter with the following main characteristics: L = 20.9 nH, Co = 18.6 nF, Cx = 3.8 nF and/s = 51.79 MHz (for Io = 100 mA), a power efficiency of 68.51 % and a occupied area of 3.77 mm2, which results in a clear improvement when the same structured design method is applied to classical buck converter. However, finally a lower switching frequency design is selected to be implemented to allow control loops operation (fs = 37.28 MHz). After providing details of the layout design, full-transistor level simulation results validate the improved performance and the efficiency model. Experimental results from an implemented IC validate the time-domain functionality of the on-chip converter.

Energy optimization of tapered buffers for CMOS on-chip switching power converters

This work presents a model to determine the power consumption of tapered buffers, validating its results with transistor-level simulations. Focusing on their application as gate drivers for high-frequency on-chip switching power converters, the need for a fall-rise time evaluation at the output of the tapered buffer is discussed. Consequently, the output fall-rise time is modeled and validated by means of simulations. Given the linear relation between the fall-rise time and the switching losses of the power MOSFET, an optimized design procedure is proposed to concurrently minimize the switching losses of the tapered buffer together with the power MOSFET switching losses. The work concludes with a design example for a 15000 /spl mu/m-width PMOS transistor, presenting an optimum tapering factor of 21, for a specific 0.35 /spl mu/m standard CMOS technology.

Efficiency-oriented switching frequency tuning for a buck switching power converter

Successful on-chip integration of a buck switching power converter concurrently requires the fulfillment of stringent specifications, namely low silicon area occupancy, low relative output ripple, proper transient response, whilst assuring high efficiency. The paper focuses on efficiency optimization of a buck converter suited to CMOS integration. Switching and conduction energy loss models are discussed, both for continuous and discontinuous conduction modes. Minimization of overall power losses yields an optimum law that continuously tunes the switching frequency as a function of load current. A practical piecewise linear approximation is proposed and applied to transient simulations and to compute overall efficiency. The work concludes by comparing the efficiency-oriented optimum frequency tuning law to that intrinsically obtained from output voltage hysteretic control. Numerical examples consider a standard CMOS 0.35 /spl mu/m technology.

Optimized design of MOS capacitors in standard CMOS technology and evaluation of their Equivalent Series Resistance for power applications

An analytical study of the MOSFET-based capacitor is presented. This highly dense capacitive structure, suited to integrated circuits, is studied specifically for power applications by providing design guidelines for achieving minimum equivalent series resistance (ESR). The work includes layout strategies in standard digital CMOS technologies to provide optimal ESR, a design procedure for a target impedance at a given frequency, as well as a performance comparison with other on-chip capacitive structures such as poly-poly and metal-metal capacitors. The results are applicable for on-chip power circuits such as output filter stages in future integrated switching power converters, switched capacitor power converters, or decoupling circuits in high-performance on-chip power distributing networks.

General-purpose ripple-based fast-scale instability prediction in switching power regulators

This paper extends the validity of a ripple-based index able to predict the frontier of fast-scale instability bifurcation in switching power converters, for the whole design-space and for different conduction modes. Hitherto a first validation of the index, based on the approximated ripple level in the PWM modulator, was carried out for a basic proportional voltage feedback PWM buck converter and for L, C, fs, Kp parameters. This article has carried out a complete design-space analysis and has found the stability boundary dependence on converter parameters. Besides, the circuit-based approach has been validated through a comparison between the proposed index and the classical analytical methods based in the linearization of the discrete-time nonlinear map. The paper also proposes improved ripple approximations, by obtaining the exact analytic ripple expression for a buck converter derived from Laplace transform. The index is also validated for a buck converter operating in DCM, through time domain simulations and bifurcation diagrams.

Predicting fast-scale instabilities in switching power converters: a ripple-based unified perspective

This paper presents a re-examination of conditions for lost of period-1 bifurcation appearance in switching power converters. A unified index based on the ripple level in the PWM modulator is able to predict first occurrence of fast-scale instability. Previous parametric design space explorations have been presented to explore the rich complex behaviour phenomena in switching power converters. The bifurcation-avoiding design-oriented index presented herein allows the designer to collect in a unified index the effect of several circuit parameters, such as input and output voltage, reactive component values and switching frequency, together with feedback parameters. The approach is validated through time domain simulations and bifurcation diagrams for a basic proportional voltage feedback PWM buck converter. Alternative topologies such as multilevel converters and interleaved parallel-connected converters, as well as more practical control methods such as dynamic compensators, current-mode control, and hysteretic control are discussed as well. Proof-of-concept experimental results are reported to demonstrate the approach

Quasi-optimum Efficiency in Output Voltage Hysteretic Control for a Buck Switching Converter with Wide Load Range

Successful on-chip integration of a buck switching power converter for battery-operated portable applications concurrently requires fulfilling stringent specifications, namely low silicon area occupancy, low relative output ripple, proper transient response whilst assuring high efficiency for a wide range of load currents. This latter key characteristic of high efficiency can be achieved not only by the power plant design but by the use of proper control methods. This work focuses in efficiency optimization of a buck converter suited to CMOS integration. Switching and conduction energy loss models are first discussed both for continuous and discontinuous conduction modes. Minimization of overall power losses yields an optimum law that continuously tunes the switching frequency as a function of load current. Being one of the simplest control methods applied to a buck converter the output voltage hysteretic control, the work then focuses in the implicit switching frequency tuning that results from the application of this control method and its impact on overall power efficiency. The paper contrasts the analytical models for the frequency variation, matched with system-level simulations, when including as non-idealities both output capacitor ESR and control delay. It is observed that for low output current values, the output voltage hysteretic control provides quasi-optimum power efficiency. Design criteria for matching both explicit optimum law and the law implicit in hysteretic control are provided, and a design procedure including output voltage ripple and capacitor value is discussed. Numerical examples throughout the paper consider a standard CMOS 0.35 mum technology. Experimental results for a low frequency prototype demonstrate the implicit switching frequency modulation of the output voltage hysteretic control

A design space exploration for integrated switching power converters

This work presents design space exploration of switching power converters focused on their monolithic implementation. An analysis in terms of the models of their main circuit elements (switching transistors, inductor and capacitor) is described. A merit figure is defined taking into account output voltage ripple, power efficiency and occupied die area. A singular point that maximizes performance is obtained, and particular simulation results for a 0.35 /spl mu/m standard CMOS technology are presented.

Ripple-reduction tuned filtering switching power converter topology

This paper presents a low-ripple topology for switching power converters that approximates the ideal ripple-free averaged dynamics by means of reactive passive tuned filters. The low-ripple characteristics can be taken advantage of to either improve the suitability of the switching power converter to supply ripple-sensitive loads, or to reduce the value of the converter main filtering capacitor. The work explores this second property in the context of pursuing further miniaturization and particularly on-chip circuit integration of a switching power converter. Experimental results for a low frequency prototype demonstrate the functionality of the proposed low-ripple topology, showing in particular a reduction of a factor of seven for the main capacitor in the converter.