Alejandro Nieto

Evaluation of real-time LBP computing in multiple architectures

Local binary pattern (LBP) is a texture operator that is used in several different computer vision applications requiring, in many cases, real-time operation in multiple computing platforms. The irruption of new video standards has increased the typical resolutions and frame rates, which need considerable computational performance. Since LBP is essentially a pixel operator that scales with image size, typical straightforward implementations are usually insufficient to meet these requirements. To identify the solutions that maximize the performance of the real-time LBP extraction, we compare a series of different implementations in terms of computational performance and energy efficiency, while analyzing the different optimizations that can be made to reach real-time performance on multiple platforms and their different available computing resources. Our contribution addresses the extensive survey of LBP implementations in different platforms that can be found in the literature. To provide for a more complete evaluation, we have implemented the LBP algorithms in several platforms, such as graphics processing units, mobile processors and a hybrid programming model image coprocessor. We have extended the evaluation of some of the solutions that can be found in previous work. In addition, we publish the source code of our implementations.

SIMD/MIMD Dynamically-Reconfigurable Architecture for High-Performance Embedded Vision Systems

Image and video processing algorithms are becoming more and more sophisticated. An efficient hardware architecture is a requirement in order to address effectively the increasing computational workload. In a context of high performance, low cost and rapid prototyping, a hybrid SIMD/MIMD architecture for image processing is proposed in this work. By reusing functional units and including a dynamically reconfigurable datapath, this architecture enables high performance devices for general image processing tasks with high application development productivity when using as part of a System-on-Chip. A 32-bit 128-unit coprocessor was prototyped on a Virtex-6 FPGA and results show a peak performance of 19.6 GOP/s.

FPGA-accelerated retinal vessel-tree extraction

This work introduces an FPGA implementation for vesseltree extraction on retinal images. The retinal vessel-tree can be used in disease diagnoses, e.g. diabetes, or in person authentication. In such cases, a portable device with a high performance may be a need. The FPGA implementation discussed here, although application-oriented, features a fully programmable SIMD architecture, allowing for an efficient realization of low-level image processing algorithms. It is mapped onto a Spartan 3, amounting to 90 processing elements. The on-chip memory utilized was 1.4MB and stores 8 gray images of 144 × 160px. The working frequency is 53MHz, allowing for a 3 × 3 convolution in less than 110μs.

Performance analysis of massively parallel embedded hardware architectures for retinal image processing

This paper examines the implementation of a retinal vessel tree extraction technique on different hardware platforms and architectures. Retinal vessel tree extraction is a representative application of those found in the domain of medical image processing. The low signal-to-noise ratio of the images leads to a large amount of low-level tasks in order to meet the accuracy requirements. In some applications, this might compromise computing speed. This paper is focused on the assessment of the performance of a retinal vessel tree extraction method on different hardware platforms. In particular, the retinal vessel tree extraction method is mapped onto a massively parallel SIMD (MP-SIMD) chip, a massively parallel processor array (MPPA) and onto an field-programmable gate arrays (FPGA).

SIMD array on FPGA for B/W image processing

This paper introduces a topographic implementation of an SIMD array for B/W image processing of 48 times 48 processing elements on an FPGA. The computation is done with Boolean and shift operators. The connectivity among processing elements is set through the classical NEWS system. The array provides the functionality of a CNNUM. The paper shows examples of algorithms and applications, and it also examines possible upscalings of the 48 times 48 array on larger FPGAs.

GPU-based segmentation of retinal blood vessels

AbstractIn this paper a fast and accurate technique for retinal vessel tree extraction is proposed. It consists of a hybrid strategy based on global image filtering and contour tracing. With the aim of increasing the computation speed, the algorithm has been tailored for efficient execution on commodity graphics processing units achieving low execution times and high speedups over the CPU execution. The performance of the proposed method was tested on publicly available databases, STARE and DRIVE, based on standard measures such as accuracy, sensitivity and specificity. Results reveal an average accuracy comparable to that reported for state-of-the art techniques. Our method performs the vascular tree segmentation of the images in the DRIVE and the STARE databases in an average of 14 ms and 18 ms, respectively. To the best of our knowledge, the proposal features the highest accuracy/performance rate in the retinal blood vessel extraction domain.

Towards the Optimal Hardware Architecture for Computer Vision

Computer Vision systems are experiencing a large increase in both range of applications and market sales (BCC Research, 2010). From industry to entertainment, Computer Vision systems are becoming more and more relevant. The research community is making a big effort to develop systems able to handle complex scenes focusing on the accuracy and the robustness of the results. New algorithms provide more advanced and comprehensive analysis of the images, expanding the set of tools to implement applications (Szeliski, 2010).

Feature detection and matching on an SIMD/MIMD hybrid embedded processor

This work presents the implementation of a feature detection and matching algorithm on an innovative SIMD/MIMD dynamically-reconfigurable architecture intended for high-performance embedded vision systems. An FPGA-based system-on-chip with a 128-unit coprocessor running at 150 MHz is able to locate a target in 320 × 240 px images in less than 1 ms. It is also shown how to map the algorithms to speedup the processing taking advantage of the different available computation modes.

A digital cellular-based system for retinal vessel-tree extraction

Nowadays, the advances in the semiconductor industry allow to include a considerable number of fully digital processing elements on a chip. These massively parallel processor arrays are already able to host cellular wave computing algorithms with acceptable time performance. In this paper we approach the implementation of an originally CNN-based algorithm for retinal vessel-tree extraction on the Ambrics parallel processor array Am2045, provided with 336 32bit processing elements. Results and measured data are included.

PRECISION: A Reconfigurable SIMD/MIMD Coprocessor for Computer Vision Systems-on-Chip

Computer vision applications have a large disparity in operations, data representation and memory access patterns from the early vision stages to the final classification and recognition stages. A hardware system for computer vision has to provide high flexibility without compromising performance, exploiting massively spatial-parallel operations but also keeping a high throughput on data-dependent and complex program flows. Furthermore, the architecture must be modular, scalable and easy to adapt to the needs of different applications. Keeping this in mind, a hybrid SIMD/MIMD architecture for embedded computer vision is proposed. It consists of a coprocessor designed to provide fast and flexible computation of demanding image processing tasks of vision applications. A 32-bit 128-unit device was prototyped on a Virtex-6 FPGA which delivers a peak performance of 19.6 GOP/s and 7.2 W of power dissipation.