Lukas Nagy

Current sensing methodology for completion detection in self-timed systems

This paper addresses an alternative approach in detecting completion of computation in asynchronous circuits. The proposed method is based on sensing the amount of consumed power supply current. It represents a simple but reliable and effective way of detecting the computation completion in this type of digital systems. The paper presents a novel topology of current sensing circuitry, explanation of the operation as well as simulation results and finally the conclusion.

130 nm CMOS Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications

In this paper, a variable gain amplifier (VGA) designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven (BD) design approach, which brings a possibility t...

Low-voltage bulk-driven variable gain amplifier in 130 nm CMOS technology

In this paper, a variable gain amplifier designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven approach, which brings a possibility to operate with low supply voltage (i.e. 0.6 V). Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no latchup risk that usually represents the main drawback of the bulk-driven approach. As an input stage, bulk driven transistors are used, which makes possible to operate in the rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide range, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications.

Current Sensing Completion Detection in deep sub-micron technologies

Current Sensing Completion Detection (CSCD) method in asynchronous circuits is addressed. Current Sensing represents a simple but effective and reliable approach to detect completion of computation in asynchronous (self-timed) systems. However, in recent deep sub-micron technologies, several challenges, such as significant influence of process variations, leakage current power dissipation with circuit in off-state, etc., have to be faced. This paper presents an overview of these undesired effects and proposes some prospective solutions.

Variable-gain amplifier for ultra-low voltage applications in 130nm CMOS technology

The paper deals with design and analysis of a variable-gain amplifier (VGA) working with a very low supply voltage, which is targeted for low-power applications. The proposed amplifier was designed using the bulk-driven approach, which is suitable for ultra-low voltage circuits. Since the power supply voltage is less than 0.6 V, there is no risk of latchup that is usually the main drawback of bulk-driven topologies. The proposed VGA was designed in 130 nm CMOS technology with the supply voltage of 0.4 V. The achieved results indicate that gain of the designed VGA can be varied from 0 dB to 18 dB. Therefore, it can be effectively used in the many applications such as automatic gain control loop with ultra-low value of supply voltage, where the dynamic range is the important parameter.

Design of low-power variable gain amplifier with linear-in-decibel dependency

The article addresses a design procedure of low-power variable gain amplifier employing so-called bulk-driven transistors in 130 nm CMOS technology, working with the power supply voltage of only 600 mV. Mentioned approach represents rather unconventional and still quite uncharted design technique. Therefore, the research potential is tremendous. The paper describes the proposed amplifier along with the achieved simulation results, process stability analysis as well as robustness over temperature variations. Additional circuit block covered by the paper is responsible for maintaining the linear gain dependency over the controlling voltage. The conclusions and experience on the design flow resulting from this research are directly incorporated into the lectures and general studying materials within the academic curriculum.

Design of digital logic cells on InAlN/GaN heterostructure

The article addresses design and development of logic gates and circuits fabricated on InAlN/GaN/Sapphire heterostructure employing an in-house technology process. Designed circuits are intended to execute the fundamental Boolean logic operations as well as the memory function covered by RS latch circuitry. The paper describes the complete design flow of logic cells, investigation and statistical simulations of their expected electrical parameters and full-custom layout representation design that will be used in the final monolithic fabrication process as a template for lithographic masks. Moreover, the development of scalable HSPICE behavioral model of standalone high electron mobility transistors (HEMT) used in the electrical simulations. Finally, pros and cons of the proposed solutions as well as challenges that need to be tackled in the future research are discussed.

3D self-heating electro-thermal model of multi-die IC

This paper addresses a development of self-heating electro-thermal model of a system-in-package (SiP) occupying several silicon dies within one IC package. Proposed model maintains very high accuracy of modeled parameters in the wide range of dynamic temperature fluctuations, which brings the thermal simulations of state-of-the-art ICs much closer to the real scenario. Presented work also introduces an alternative approach to simulating electro-thermal properties of selected SiP using pseudo-transient simulations which radically reduces required simulation time.

Design of E/D-mode InAlN/GaN HFET inverter and its robustness analysis

This article describes the design procedure towards a robust digital inverter that is intended to be fabricated on InAlN/GaN material heterostructure. Heterojunction field effect transistors (HFETs), regardless the material used, exhibit exceptional power delivery at high frequencies and also outstanding capability to withstand the operation in a very harsh environment. These properties make HFET transistors an excellent candidate for the future electronic applications. Effective utilization of such excellent properties requires monolithic integration of E-mode and D-mode transistors on a single die. However, the fabrication process of the heterostructures themselves and HFET transistors are not that mature and reliable as it is in the case of other materials used in microelectronics. In this paper, we describe the design of a basic logic circuit using both E-mode and D-mode HFETs as well as design of the output buffer. Due to immaturity of the technological process and physical constraints, the properties of depletion load based inverters and various output buffers are investigated in details with regard to the robustness.

3-D electrothermal device/circuit simulation of DC-DC converter module in multi-die IC

Presented work introduces automated interaction of SDevice and HSPICE for fast 3-D electrothermal simulation. The proposed methodology maintains a very high accuracy of the modelled parameters in a wide range of dynamic temperature fluctuations, which brings the thermal simulations much closer to the real state. The designed electrothermal simulation is developed for Synopsys TCAD Sentaurus environment. The main goal is decreasing the simulation time for complex 3-D devices. A DC-DC converter module in a multi-die integrated circuit is used as an example to perform validation of the designed electrothermal simulation. The features and limitations of the method are analyzed and presented.