Alessia Pavan

Oxide Thinning in Shallow Trench Isolation

Aim of this work is to study the thinning of thick HV gate oxides in flash and embedded flash processes due to the shallow trench isolation (STI) induced stress on oxide growth

Anomalous gate oxide conduction on isolation edges: analysis and process optimization

Abstract In this paper we report a detailed characterization of anomalous gate oxide conduction on isolation edges. Previously, it was shown that gate oxide can feature severe thickness variation [Liu et al., Proceedings of VLSI Symposium, 1999, p. 75; Mat. Res. Soc. Symp. 611 (2000) C4.1.1] near the top corner of the shallow trench isolation. Here, we show that this can significantly impact the tunnel I–V characteristics of gate oxide, with implications for the device performance uniformity and reliability. Comparing experimental data with accurate tunnel current simulation we demonstrate that this anomalous conduction is due to a double effect of oxide thinning and rounding of the poly/oxide interface. Furthermore, we study the impact of many process parameters on this anomalous leakage. We show that, by optimizing several process steps, it is possible to avoid this problem. Possible physical causes of this phenomenon are also addressed.