Daniela Brazzelli

Stress induced leakage current and bulk oxide trapping: temperature evolution

A key issue for flash cell scaling down is the reduction of tunnel oxide thickness. This is mainly limited by the information loss induced by the higher gate leakage current after cycling, becoming critical below 10 nm thickness. Multiple trap assisted tunneling has been proposed to model the conduction of degraded thick oxides, but it is not yet clear the nature of the associated defects. Data reported here are obtained on flat area capacitors with a standard full CMOS process with STI (shallow trench isolation) and dual-gate technology. Tunnel oxides of 8 nm thickness have been grown with different oxidation technologies. The measurement procedure is based on three steps to estimate the stable charge (Q/sub stable/), and its position, and the stationary SILC (stress induced leakage current) measured at a fixed field and extrapolated by the tunneling front model.

Charge trapping mechanism under dynamic stress and its effect on failure time [gate oxides]

The aim of this work was to investigate the effect of dynamic versus DC voltage stress applied to thin oxides. A longer lifetime was observed under pulsed stress at high electric fields. When increasing the frequency, we noticed an increment of lifetime and a different trapped charge location, regardless of the stress polarity. To detect the charge trapping evolution under pulsed stress, we used a new experimental procedure. Fast transitory phenomena detected using this technique are interpreted as charging and discharging of positive traps located in the anodic region. The consequent reduction of the effective positive charge allows us to explain the lifetime enhancement and the charge trapping evolution. We also compared the behaviour under pulsed stress of oxides grown in dry or steam environments. The lifetime increase is more relevant in dry oxides showing a correlation between the interface quality and the oxide reliability in dynamic mode.

Oxide Thinning in Shallow Trench Isolation

Aim of this work is to study the thinning of thick HV gate oxides in flash and embedded flash processes due to the shallow trench isolation (STI) induced stress on oxide growth

Impact of interface and bulk trapped charges on transistor reliability

Oxide reliability is a key issue and the main topic of several recent works. We study the impact of gate oxide stress on transistor performances following a methodology similar to oxide lifetime characterisation in capacitors. A universal trend for degradation of the threshold voltage and drain saturation current with injected charge is observed and the impact of boron on trapping enhancement has been separated by comparing n-MOS and p-MOS.

Anomalous gate oxide conduction on isolation edges: analysis and process optimization

Abstract In this paper we report a detailed characterization of anomalous gate oxide conduction on isolation edges. Previously, it was shown that gate oxide can feature severe thickness variation [Liu et al., Proceedings of VLSI Symposium, 1999, p. 75; Mat. Res. Soc. Symp. 611 (2000) C4.1.1] near the top corner of the shallow trench isolation. Here, we show that this can significantly impact the tunnel I–V characteristics of gate oxide, with implications for the device performance uniformity and reliability. Comparing experimental data with accurate tunnel current simulation we demonstrate that this anomalous conduction is due to a double effect of oxide thinning and rounding of the poly/oxide interface. Furthermore, we study the impact of many process parameters on this anomalous leakage. We show that, by optimizing several process steps, it is possible to avoid this problem. Possible physical causes of this phenomenon are also addressed.

Methodology for Word Line-Contact Dielectric Characterization in Flash Normemories

Aim of this work is to study the reliability of the dielectric between cell control gate and drain contact. Conduction characteristics and reliability under high field stress are investigated. The large spread in this dielectric thickness because of mask misalignment makes the usual reliability procedures very difficult to be applied. Results relative to fast and long reliability measurements are discussed, proposing a method for the evaluation of the spread between control gate and drain contact. Moreover, this methodology allows a screening of the structures with a too critical mask misalignment, or with a poor dielectric quality which could cause memory failures during cycling