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Dive into the research topics where Cesare Clementi is active.

Publication


Featured researches published by Cesare Clementi.


Microelectronics Reliability | 1998

The impact of F contamination induced by the process on the gate oxide reliability

G. Ghidini; Cesare Clementi; D Drera; F Maugain

The effects of F contaminants introduced by the CVD WSi2 deposition and diffused to the gate oxide interfaces by the thermal treatment performed during the process have been analyzed. High field stresses showed a degradation of the quality of the oxides contaminated by fluorine, but decreasing the stress field below a critical value of 10.5 MV/cm no more effect of fluorine on the gate oxide reliability was detectable.


Microelectronics Reliability | 1998

Influence of charge trapping on oxide scaling down

G. Ghidini; Mauro Alessandri; Cesare Clementi; F. Pellizzer

Abstract The aim of this work is the characterization, in terms of trapped charge and charge to breakdown, of the quality of an oxide with reduced thickness. A comparison between two evaluation methods, the widely used exponentially ramped current stress (ERCS) and the constant current stress (CCS), is established obtaining contradictory results. A measurement of the charge trapped in the oxide bulk is performed by sensing the modification of the Fowler–Nordheim barrier under constant current stress. Using this technique it is possible to correlate the charge trapping characteristics with the charge to breakdown and to explain the inconsistencies.


Solid-state Electronics | 1997

Feasibility of steam tunnel oxide for advanced non volatile memories

G. Ghidini; Marina Tosi; Cesare Clementi

Abstract In order to reduce dopant diffusion to obtain device scaling, a decrease of any thermal treatment is required. Therefore, to substitute dry thermal oxides for tunnel application in Flash Memories, the possibility of using steam oxides grown at low temperatures was studied, considering, in addition, scaling of these oxides for future generations. Results concerning oxide reliability and charge trapping for elementary structures are presented and correlated with device performance.


Archive | 1996

Process for forming an integrated circuit comprising non-volatile memory cells and side transistors of at least two different types, and corresponding IC

Cesare Clementi; G. Ghidini; Carlo Riva


Archive | 1999

Process for forming an integrated circuit comprising non-volatile memory cells and side transistors and corresponding IC

Cesare Clementi; G. Ghidini; Carlo Riva


Archive | 1993

Method of making an EPROM cell with a readily scalable interpoly dielectric

Cesare Clementi; G. Ghidini; Marina Tosi


Archive | 1996

Method of manufacturing a MOS integrated circuit having components with different dielectrics

G. Ghidini; Cesare Clementi


Archive | 1995

EPROM cell with a readily scalable interpoly dielectric

Cesare Clementi; G. Ghidini; Marina Tosi


Archive | 1993

Method of fabricating integrated devices

Giuseppe Crisenza; Cesare Clementi


Archive | 1995

Method of fabricating non-volatile memories with overlapping layers

Giuseppe Crisenza; Cesare Clementi

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