Livio Baldi

A scalable single poly EEPROM cell for embedded memory applications

An increasing number of Integrated Circuits requires the embedding of a limited amount (up to 16-64 kbits) of EEPROM memory. For this application, low process complexity, robust structure and good reliability are more important than small cell size. In this paper we present the design and characterization of a single poly EEPROM cell, optimized for embedded applications, and characterized by a good shrink potential. A cell area of 68.7¿m2 has been obtained in 0.7¿m technology, and electrical characterization has shown the possibility of achieving a programming time of less than 1 ms, while an endurance of more than 10 million cycles has been achieved at 125°C, with a programming time of 2 ms. By further shrink of the same basic layout, cell areas of 55¿m2 and 44¿m2 have been obtained, and the similar programming and endurance performances have been demonstrated.

Design methodologies and architecture solutions for high-performance interconnects

In deep sub-micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex system-on-chip (SoC) designs. For technologies of 0.25 /spl mu/m and below, wiring capacitance dominates gate capacitance, thus rapidly increasing the interconnect-induced delay. Moreover, the coupling capacitance becomes a significant portion of the on-chip total wiring capacitance, and coupling between adjacent wires cannot be considered as a second-order effect any longer. As a consequence, the traditional top-down design methodology is ineffective, since the actual wiring delays can be computed only after layout parasitic extraction, when the physical design is completed. Fixing all the timing violations often requires several time-consuming iterations of logical and physical design, and it is essentially a trial-and-error approach. Increasingly tighter time-to-market requirements dictate that interconnect parasitics must be taken into account during all phases of the design flow, at different level of abstractions. However, given the aggressive technology scaling trends and the growing design complexity, this approach is only temporarily ameliorate the interconnect problem. We believe that in order to achieve gigascale designs in the nanometer regime, a novel design paradigm, based on new forms of regularity and newly created IP (intellectual property) blocks must be developed, to provide a direct path from system-level architectural exploration to physical implementation.

VLSI technologies: High performers and workhorses

The evolution of integrated circuit has been characterized in the past three decades by an exponential growth, both in performances and in circuit complexity, and it is showing no sign of slowing down. Several families of technologies have contributed to this explosive development: bipolar, GaAs and MOS, but only the last one has emerged as suitable for VLSI. However, each of the three has found its special field of application and is bringing its contribute to the total growth of circuit integration. It is very likely that all three shall coexist also in the next future, and will benefit from a mutual exchange of basic techniques. CMOS however will remain the main technology for VLSI, due to low power dissipation, flexibility and relatively low complexity. The critical issues which could hinder the further development of CMOS technology in the submicron range are essentially related to reliability, due to the increase in electric field and power density. The proposed solutions will probably imply new standards in supply voltages and slow down the progress in device speed.