Alex G. Dickinson

Adiabatic dynamic logic

With adiabatic techniques for capacitor charging, theory suggests that it should be possible to build gates with arbitrarily small energy dissipation. In practice, the complexity of adiabatic approaches has made them impractical. We describe a new CMOS logic family-adiabatic dynamic logic (ADL)-that is the result of combining adiabatic theory with conventional CMOS dynamic logic. ADL gates are simple, general, readily cascadable, and may be fabricated in a standard CMOS process. A chain of 1000 ADL inverters has been constructed in 0.9 /spl mu/m CMOS and successfully tested at 250 MHz. This result, together with comprehensive circuit simulation, suggest that ADL offers an order of magnitude reduction in power consumption over conventional CMOS circuitry. >

Camera on a chip

Recent advances in video compression and digital networking technology, combined with the ever increasing power of PCs and workstations, are creating enormous opportunities to develop new multimedia products and services built upon sophisticated voice, data, image and video processing. This will create a significant demand for compact, low-cost, low-power electronic cameras for video and still image capture. These cameras will be a standard peripheral on all PCs bundled for multimedia applications. Given that in excess of 60M PCs will be sold this year, a sizable new market for electronic cameras is being created.

A 256/spl times/256 CMOS active pixel image sensor with motion detection

This 256/spl times/256 active pixel sensor (APS) is designed for consumer multimedia applications requiring low-cost, high-functionality, compact cameras capable of acquiring high-quality images at video frame rates. This sensor allows random access of the image data, permitting a simple implementation of electronic pan and zoom. Use in portable equipment is simplified by standard operating voltages and low power (80mW@5V, 20mW@3.3V). Fabrication in a standard CMOS process allows the integration of a variety of new and existing digital circuits with the image sensor. In addition, by making use of the implicit dynamic frame buffer provided by the active pixel structure, the sensor can generate a signal that represents the difference between sequential frames. This may be used for motion detection, image stabilization, and compression purposes.

Standard CMOS active pixel image sensors for multimedia applications

The task of image acquisition is completely dominated by CCD-based sensors fabricated on specialized process lines. These devices provide an essentially passive means of detecting photons and moving image data across chip. We argue that line widths in standard CMOS have been reduced to the point where it is practical to locate transistors-and hence provide gain-within each detector of an imager fabricated in CMOS. In this paper we describe the image sensors we have been building in this technology. They use far less power, permit random access and can be integrated with arbitrary digital CMOS logic to create low cost single chip video cameras with advanced functionality. Ongoing work includes the development of a color filter array process and the fabrication of a 1024/spl times/1024 pixel sensor for multimedia video and document capture applications.

Free-space optical interconnection scheme.

As integrated circuit linewidths are reduced, single chip system functionality and speed increase. Conventional electronic chip input/output does not scale with this trend: bonding pad sizes and off-chip capacitive loads remain essentially constant. The shortage of chip interconnect capability has become critical. Integrated free-space optical interconnect has the potential to overcome this problem by providing a large number of high speed connections between chips. This paper describes methods for performing free-space intermodule optical interconnections within a digital electronic computer utilizing large arrays of light beams. A particular architecture and its ongoing implementation with integrated components are discussed.

An integrated free space optical bus

As integrated circuit linewidths are reduced, single-chip system functionality and speed increase. Conventional electronic chip input/output does not follow this trend: bonding pad sizes and off chip capacitive loads remain essentially constant. Shortage of chip interconnect capability has become critical. Integrated free-space optical interconnect has the potential to overcome this problem by providing a large number of high-speed connections between chips. A description is given of the application of free-space optics, quantum-well modulators, and CMOS photodetectors to this task.<<ETX>>

A systolic architecture for high speed pipelined memories

Proposes a scalable memory architecture that maintains a high data rate, independent of address sequence and memory size. It is suitable for applications where throughput is of primary importance and access latency is tolerable. A rectangular array of memory blocks is pipelined to build a memory with an operating frequency determined only by the access time of a single block. This is independent of the number of blocks because address and data communication is localized to adjacent memory blocks. Rather than sacrificing speed for memory size, the new approach scales to provide high-throughput random access memories of very large size with some increase in latency.<<ETX>>

A scalable pipelined architecture for fast buffer SRAMs

The design of synchronous buffer SRAMs for packet switching and signal processing applications is described. Called scalable cellular RAM (SCRAM), the approach configures memory blocks in a 2-D array with fully pipelined address and data distribution. The memory is scalable in that the access frequency is determined by the access time of a single block and is independent of the number of blocks. An experimental 0.5 /spl mu/m CMOS 256 Kb SCRAM chip is described that operates at 240 MHz. Simulation results show that larger arrays are feasible using the suggested power reduction and redundancy techniques.

256 x 256 CMOS active pixel image sensor

A 256 X 256 CMOS photo-gate active pixel image sensor is presented. The image sensor uses four MOS transistors within each pixel to buffer the photo-signal, enhance sensitivity, and suppress noise. The pixel size is 20 micrometers X 20 micrometers and was implemented in a standard digital 0.9 micrometers single-polysilicon, double-metal, n-well CMOS process; leading to 25% fill-factor. Row and column decoders and counters are monolithically integrated as well as per column analog signal correlated double-sampling (CDS) processors, yielding a total chip size of approximately 4.5 mm X 5.0 mm. The image sensor features random accessibility and can be employed for electronic panning applications. It is powered from a single 5.0 V source. At 5.0 V power supply, the video signal saturation level is approximately 1,200 mV with rms read-out noise level of approximately 300 (mu) V, yielding a dynamic range of 72 dB (12 bits). The read-out sensitivity is approximately 6.75 (mu) V per electron, indicating a read-out node capacitance of approximately 24 fF which is consistent with the extracted value. The measured dark current (at room temperature) is approximately 160 mV/s, equivalent to 3.3 nA/cm 2 . The raw fixed pattern noise (exhibited as column-wise streaks) is approximately 20 mV (peak-to-peak) or approximately 1.67% of saturation level. At 15 frames per second, the power dissipation is approximately 75 mW.

A mismatch free CMOS dynamic voltage comparator

This paper describes an analog voltage comparator. It uses a current-mode approach for the storage of one input and reuse of the same transistors for both analog inputs, thus avoiding the problem of transistor mismatch encountered in differential structures. The circuit has been fabricated in a digital 0.9 /spl mu/m CMOS process and was tested with a power supply of 1.5 V. The measured offset is 1 mV.