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Dive into the research topics where Chung-Yi Yu is active.

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Featured researches published by Chung-Yi Yu.


international electron devices meeting | 2015

A next generation CMOS-compatible GaN-on-Si transistors for high efficiency energy systems

K.-Y. Roy Wong; Man-Ho Kwan; Fu-Wei Yao; M.W. Tsai; Yen-Chun Lin; Yi-Hsien Chang; Po-Chih Chen; R.-Y. Su; J. L. Yu; Fu-Chih Yang; G. P. Lansbergen; Chih-Wen Hsiung; Y.-A. Lai; K.-L. Chiu; Chang‐Nan Chen; M.-C. Lin; H.-Y. Wu; C.-H. Chiang; Sheng-Da Liu; Han-Chin Chiu; P.-C. Liu; Claire Chen; Chung-Yi Yu; Chia-Shiung Tsai; C.-B. Wu; B. Lin; M.-H. Chang; Jan-Wen You; S.-P. Wang; L.-C. Chen

CMOS-compatible 100 V / 650 V enhancement-mode high electron mobility transistors (E-HEMTs) and 650 V depletion-mode MISFET (D-MISFET) are fabricated on 6-inch GaN-on-Si wafers. These devices show excellent power converter switching performances. Both 100 V and 650 V E-HEMTs had passed industrial reliability qualifications. The importance of bulk leakage, interface quality and gate trapping in dynamic on-resistance is figured out. The device with optimized processes shows a significant reduction of the dynamic on-resistance degradation.


international electron devices meeting | 2014

CMOS-compatible GaN-on-Si field-effect transistors for high voltage power applications

Man Ho Kwan; King-Yuen Wong; Y. S. Lin; Fu-Wei Yao; M.W. Tsai; Yi-Hsien Chang; P. C. Chen; Ru-Yi Su; Cheng-Hsien Wu; J. L. Yu; F. J. Yang; G. P. Lansbergen; H.-Y. Wu; M.-C. Lin; C.-B. Wu; Y.-A. Lai; Chih-Wen Hsiung; P.-C. Liu; H.-C. Chiu; Ching-Ray Chen; Chung-Yi Yu; Hong-Nien Lin; M.-H. Chang; S.-P. Wang; L.-C. Chen; J. L. Tsai; H. C. Tuan; Alex Kalnitsky

CMOS-compatible 100/650 V enhancement-mode FETs and 650 V depletion-mode MISFETs are fabricated on 6-inch AlGaN/GaN-on-Si wafers. They show high breakdown voltage and low specific on-resistance with good wafer uniformity. The importance of epitaxial quality is figured out in a key industrial item: high-temperature-reverse-bias-stress-induced on-state drain curent degradation. Optimization of epitaxial layers shows significant improvement of device reliability.


international symposium on power semiconductor devices and ic's | 2014

AlGaN/GaN MIS-HFET with improvement in high temperature gate bias stress-induced reliability

King-Yuen Wong; Yen-Chun Lin; Chih-Wen Hsiung; G. P. Lansbergen; M.-C. Lin; Fu-Wei Yao; C. J. Yu; Po-Chih Chen; R.-Y. Su; J. L. Yu; P.-C. Liu; Claire Chen; C.-H. Chiang; Han-Chin Chiu; S. D. Liu; Y.-A. Lai; Chung-Yi Yu; Fu-Chih Yang; C. L. Tsai; Chia-Shiung Tsai; Xiaomeng Chen; H. C. Tuan; Alex Kalnitsky

CMOS-compatible GaN-on-silicon technology with excellent D-mode MISHFET performance is realized. A low specific contact resistance R<sub>c</sub> (0.35 Ω-mm) is achieved by Au-free process. MIS-HFET with a gate-drain distance (L<sub>GD</sub>) of 15 μm exhibits a large breakdown voltage (BV) (980 V with grounded substrate) and a low specific on-resistance (R <sub>ON</sub>,<sub>sp</sub>) (1.45 mΩ-cm<sup>2</sup>). The importance of epitaxial quality in a key industrial qualification item: high temperature gate bias (HTGB) stress-induced voltage instability issue is figured out and a breakthrough by optimizing GaN epitaxial layer for improvement of MIS-HFET is demonstrated. A low V<sub>th</sub> shift of the optimized MIS-HFET is achieved ~ 0.14V with qualification stress condition V<sub>G</sub> of -15 V at ambient temperature of 150 oC for 128 hours.


Archive | 2015

III-V Multi-Channel FinFETs

Hung-Ta Lin; Chun-Feng Nieh; Chung-Yi Yu; Chi-Ming Chen


Archive | 2011

GALLIUM NITRIDE GROWTH METHOD ON SILICON SUBSTRATE

Chi-Ming Chen; Po-Chun Liu; Hung-Ta Lin; Chung-Yi Yu; Chia-Shiung Tsai; Ho-Yung David Hwang


Archive | 2011

Substrate breakdown voltage improvement for group iii-nitride on a silicon substrate

Chi-Ming Chen; Po-Chun Liu; Hung-Ta Lin; Chin-Cheng Chang; Chung-Yi Yu; Chia-Shiung Tsai; Ho-Yung David Hwang


Archive | 2011

III-nitride growth method on silicon substrate

Chi-Ming Chen; Po-Chun Liu; Hung-Ta Lin; Chin-Cheng Chang; Chung-Yi Yu; Chia-Shiung Tsai; Ho-Yung David Hwang


Archive | 2012

Graded Aluminum-Gallium-Nitride and Superlattice Buffer Layer for III-V Nitride Layer on Silicon Substrate

Chi-Ming Chen; Po-Chun Liu; Chung-Yi Yu


Archive | 2010

Reducing wafer distortion through a low CTE layer

Chi-Ming Chen; Chung-Yi Yu; Chia-Shiung Tsai; Ho-Yung David Hwang


Archive | 2010

SILICON WAFER STRENGTH ENHANCEMENT

Chi-Ming Chen; Chung-Yi Yu; Chia-Shiung Tsai; Ho-Yung David Hwang; Alexander Kalnitsky

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