Erwin J. Prinz

Silicon nanocrystal non-volatile memory for embedded memory scaling

In this paper, we present key features of silicon nanocrystal memory technology. This technology is an attractive candidate for scaling of embedded non-volatile memory (NVM). By replacing a continuous floating gate by electrically isolated silicon nanocrystals embedded in an oxide, this technology mitigates the vulnerability of charge loss through tunnel oxide defects and hence permits tunnel oxide and operating voltage scaling along with accompanied process simplifications. However, going to discrete nanocrystals brings new physical attributes that include the impact of Coulomb blockade or charge confinement, science of formation of nanocrystals of correct size and density and the role of fluctuations, all of which are addressed in this paper using single memory cell and memory array data.

The zen of nonvolatile memories

Silicon technology based nonvolatile memories (NVM) have achieved widespread adoption for code and data storage applications. In the last 30 years, the traditional floating gate bitcell has been scaled following Moores law, but recently scaling limits have been encountered which will require alternative solutions after the 65 nm technology node. Both evolutionary and novel solutions are being pursued in the industry. While the traditional floating gate technology will scale to the 65 nm node, novel device structures and array architectures will be needed past that node

A 90nm Embedded 2-Bit Per Cell Nanocrystal Flash EEPROM

A two bit/cell embedded nanocrystal bitcell with low write current SSI program and tunnel erase in which nanocrystals are located under dedicated control gates has been demonstrated. Write bias conditions which mitigate gate disturb in a top erase capable bitcell have been confirmed

Gate Disturb Reduction in a Silicon Nanocrystal Flash EEPROM by Means of Natural Threshold Voltage Reduction

Introduction As CMOS technology is scaled to the 90nm node and beyond, silicon nanocrystal nonvolatile memories are receiving increased attention as a replacement for floating gate nonvolatile memories [1, 2]. The thin dielectrics in these memories can lead to excessive gate disturb during the read operation. Of primary concern is the loss of electrons of the program state to the gate through the top oxide overlying the nanocrystals. This loss is the result of tunneling due to the high electric field between the gate and the nanocrystals. It has been shown that reducing the natural threshold voltage (Vt,nat) of the memory cell leads to a reduction in gate disturb [3]. Simple reduction of the Vt,nat by decreasing the substrate doping concentration can result in severely degraded short channel performance, as well as degraded hot carrier injection (HCI) performance during the program operation. Thus, it is desired to construct a substrate doping profile with a light surface concentration to obtain a low Vt,nat, and a heavy doping concentration just below the surface to provide robust short channel performance and good HCI programmability.

Effects of heavy ion exposure on nanocrystal nonvolatile memory

Advanced nanocrystal nonvolatile memories have been exposed to heavy ion bombardment. They appear to be promising candidates for future spacecraft electronics.