Craig T. Swift

A new SONOS memory using source-side injection for programming

We reported a new polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory using channel hot electron injection for high-speed programming. For the first time, we demonstrated that source-side injection technique, which is commonly used in floating gate nonvolatile memories for its high programming efficiency, can also be used in a SONOS device for achieving high-speed programming. Erase of the device is achieved by tunneling of electrons through the thin top oxide of the ONO charge storage stack. Since the thin top oxide is grown from the nitride layer, the self-saturated nature of the oxidation allows better thickness control. Endurance characteristics indicates that quality of the thin top grown from nitride is as good as the tunnel oxide grown from the silicon substrate. By increasing the top oxide thickness, it is possible to achieve ten years of retention requirement. The self-aligned sidewall gate structure allows small cell size for high density applications.

An embedded 90 nm SONOS nonvolatile memory utilizing hot electron programming and uniform tunnel erase

In this work, a new compact SONOS Flash EEPROM device with fast programming, high reliability, and uniform erase is demonstrated. This device has been embedded into a 90 nm high performance CMOS logic process with an advanced copper backend. This device utilizes hot electron injection for programming and uniform channel tunneling for erase. Uniform tunnel erase prevents residual electron build up over the channel and avoids the reliability concerns of hot hole erase. A single bit is stored in each nonvolatile memory transistor.

A 6 V embedded 90 nm silicon nanocrystal nonvolatile memory

The first functional 6 V, 4 Mb silicon nanocrystal based nonvolatile memory arrays using conventional 90 nm and 0.25 /spl mu/m process technologies have been produced. The technology can be programmed and erased using conventional techniques in floating gate memories and can substantially reduce the cost of embedded flash at the 90 nm node and beyond.

A 32-bit RISC microcontroller with 448K bytes of embedded flash memory

This paper describes a sub-half micron embedded flash EEPROM developed for high speed microcontroller applications. A 32-bit RISC microcontroller with 448 kbytes (3.67 Mbits) of embedded flash EEPROM is presented. High density flash memory is achieved by utilizing a single transistor NOR type cell that employs Fowler-Nordheim electron tunneling for both program and erase. The high density flash EEPROM is integrated into a high performance logic process with dual gate oxides for high performance and high voltage transistors. The array program time is greatly reduced by employing a highly parallel program operation, and data throughput is greatly enhanced by a page mode operation. Operating at 40 MHz, the embedded flash memory has an on-chip off-page access time of under 38 ns and on-page access time of under 13 ns.

Oxide charge trapping and HCI susceptibility of a submicron CMOS dual-poly (N/sup +//P/sup +/) gate technology

Gate-oxide charge trapping and hot-carrier injection (HCI) susceptibility of a submicrometer CMOS dual-poly (n/sup +//p/sup +/) gate, Ti-salicide, double-metal technology are discussed. The Si-SiO/sub 2/ interface property is believed to be modified by the p/sup +/ poly gate process, possibly due to boron penetration from the p/sup +/ polysilicon into the gate oxide. This accounts for the observed reduction in hole trapping during constant-current stress of the p/sup +/ poly gate capacitors and the large critical energy for interface trap generation during HCI stress of the p/sup +/ poly gate transistors. A general empirical relationship between the HCI power law parameters A (the precoefficient) and n (the power index) was obtained for both n-channel p-channel devices to describe the stress-time dependent degradation. Using the derived MOSFET lifetime, the limiting device type for this submicrometer CMOS dual-poly gate technology has also been determined. >