James D. Burnett

One transistor DRAM cell structure and method for forming

INTERLAYER DIELECTRIC UNDER STRESS FOR AN INTEGRATED CIRCUIT

Process for forming an electronic device including a fin-type structure

Single transistor memory cell with reduced programming voltages

Integrated circuit having a memory with low voltage read/write operation

Single transistor memory cell with reduced recombination rates

VOLTAGE-BASED MEMORY SIZE SCALING IN A DATA PROCESSING SYSTEM

Apparatus and method for adjusting an operating parameter of an integrated circuit

Electronic device including a fin-type transistor structure and a process for forming the electronic device

Integrated circuit using FinFETs and having a static random access memory (SRAM)