Alexandra Aguiar

Embedded systems' virtualization: The next challenge?

Traditionally, virtualization has been adopted by enterprise industry aiming to make better use of general purpose multi-core processors and its use in embedded systems (ES) seemed to be both a distant and unnecessary reality. However, with the rise of each more powerful multiprocessed ESs, virtualization brings an opportunity to use simultaneously several operating systems (OS) besides offering more secure systems and even an easier way to reuse legacy software. Although ESs have increasingly bigger computational power, they are still far more restricted than general purpose computers, especially in terms of area, memory and power consumption. Therefore, is it possible to use virtualization — a technique that typically demands robust systems — in powerful yet restricted current embedded systems? In this paper we show why the answer should be yes.

Hellfire: A design framework for critical embedded systems' applications

Hellfire framework (HellfireFW) presents a design flow for the design of MPSoC based critical embedded systems. Health-care electronics, security equipment and space aircraft are examples of such systems that, besides presenting typical embedded systems constraints, bring new design challenges as their restrictions are even tighter in terms of area, power consumption and high-performance in distributed computing involving real-time processing requirement. In this paper, we present the Hellfire framework, which offers an integrated tool-flow in which design space exploration (DSE), OS customization and static and dynamic application mapping are highly automated. The designer can develop embedded sequential and parallel applications while evaluating how design decisions impact in overall system behavior, in terms of static and dynamic task mapping, performance, deadline miss ratio, communication traffic and energy consumption. Results show that: i) our solution is suitable for hard real-time critical embedded systems, in terms of real-time scheduling and OS overhead; ii) an accurate analysis of critical embedded applications in terms of deadline miss ratio can be done using HellfireFW; iii) designer can better decide which architecture is more suitable for the application; iv) different HW/SW solutions by configuring both the RTOS and the HW platform can be simulated.

Partitioning and dynamic mapping evaluation for energy consumption minimization on NoC-based MPSoC

Software complexity has increased considerably over recent years, needing special target architectures as NoC-based MPSoCs to fulfill the heavy storage, communication and computation requirements. The design of these systems requires efficient methodologies aggregating partitioning and mapping. In these sense, this paper explores partitioning and mapping influence on energy consumption of homogeneous NoC-Based MPSoC. In addition, it compares two strategies to achieve efficient dynamic mappings: one that map tasks directly onto processors and another one that applies a previous static task-partitioning and uses this information to choose the dynamic task mapping. Experiments with various synthetic and four embedded applications show the efficiency of the second strategy that minimizes an average of 23.5% on energy consumption.

High-Level Estimation of Execution Time and Energy Consumption for Fast Homogeneous MPSoCs Prototyping

In order to fulfill the increasing performance requirements, complex embedded systems design makes use of many processors communicating through efficient infrastructures, performing multiprocessor-systems-on-chip (MPSoCs). Issues related to execution time and energy consumption estimations become more relevant during the design stage of such systems, in order to verify their compliance with the specification. Different estimation techniques have been proposed, including analytical and simulation-based methods. Analytical methods are faster than simulation-based methods, but the system description is more complex, and sometimes this approach conducts to low precision results misleading future design steps. On the other hand, the more accurate results achieved with simulation-based method, using low-level descriptions, may delay the design making it unfeasible or at least affecting the time-to-market. In this context, improvements in simulation-based methods become pertinent. This paper presents a study, a design flow and a tool for high-level simulation-based estimation of execution time and energy consumption of homogeneous MPSoCs. The implemented tool, which employs the methodology presented in this paper, improved dramatically simulation times when compared to RTL simulations. The preliminary results show that, for some cases, the RTL simulation takes tens hours while the implemented tool gets close estimation results in just few seconds.

Embedded virtualization for the next generation of cluster-based MPSoCs

Classic MPSoCs tend to be fully implemented using a single communication approach. However, recent efforts have shown a new promising multiprocessor system-on-chip infrastructure: cluster-based or clustered MPSoC. This infrastructure adopts hybrid interconnection schemes where both buses and NoCs are used in a concomitant way. The main idea is to decrease the size and complexity of the NoC by using bus based communication systems at each local port. For example, while in a classic approach a 16 processor NoC might be formed in a 4 × 4 arrangement, in cluster-based MPSoCs a 2 × 2 NoC is employed and each router connected to a local port contains buses that carry 4 processors. Nevertheless, although good results have been reached using this approach, the implementation of wrappers to connect the local router port to the bus can be complex. Therefore, we propose in this work the use of embedded virtualization, another current promising technique, to achieve similar results to cluster based MPSoCs without the need for wrappers besides providing a decreased area usage.

Partitioning and mapping on NoC-Based MPSoC: an energy consumption saving approach

Software complexity has increased considerably over recent years, needing special target architectures as MPSoCs to fulfill the heavy memory, communication and computation requirements. Nevertheless, the use of MPSoCs has brought attention to the need for effective methods and tools for parallel software development. Methodologies aggregating partitioning and mapping are normally employed to fulfill the heavy requirements of such systems. This paper explores task-partitioning and processor-mapping methods on homogeneous NoC-Based MPSoC. The effect of both on applications energy consumption is explored alone and jointly. Experiments with several synthetic and four real applications show that the energy consumption is reduced up to 18%, 31.8% or 38.1% when applying partitioning, mapping or both, respectively.

Current techniques and future trends in embedded system's virtualization

Traditionally, virtualization has been adopted by enterprise industry to make better use of the general purpose processors (single and multicore) besides improving the utilization of existing computational resources, especially in data centers. Until recently, its use in embedded systems (ESs) seemed to be a distant, unnecessary, and unfeasible reality. However, with the rise of each more powerful multiprocessed ESs, typically implemented as multiprocessor system‐on‐chip, virtualization has become a very promising technique to achieve and improve functionalities in future multiprocessor system‐on‐chips. One of the main advantages of virtualizing ESs is to improve the software design quality because legacy software can be reused along with newer applications. Also, we have the classic use cases, such as allowing several operating systems (OSs) to work in the same physical resource, simultaneously. Still, we can provide more secure ESs by splitting the system into user application OS and security certified OS, for instance. Moreover, depending on the way that embedded virtualization is employed, it may be even possible to reduce manufacturing costs and energy consumption levels. However, it is well understood that although ESs deal with increasingly more powerful solutions, they are still far more restricted than general purpose computers, especially in terms of area, memory size, and power consumption. In this article, we provide an extensive analysis of what is being currently offered as embedded virtualization solution, the pros and cons, besides presenting an innovative proposal regarding virtualization for restricted embedded architectures and its possible advantages. Copyright

Adding virtualization support in MIPS 4Kc-based MPSoCs

Virtualization has emerged as a feasible technique for Embedded Systems, providing safer platforms, improving design quality and reducing manufacturing costs. However, its inherit overhead still prevent its wide adoption. Most of the current attempts use the para-virtualization technique that imposes the cost of performing comprehensive changes in the guest OS. We propose the adoption of full-virtualization for MPSoCs, where no guest OS changes are required and, in order to reduce known virtualization overheads, we propose some hardware modifications to a MIPS-based architecture. We conducted experiments that demonstrate our proposal by comparing its processing and communication overheads against a non-virtualized solution.

On the design space exploration through the Hellfire Framework

Embedded systems have faced dramatic and extensive changes throughout the past years leading to each more complex designs. Thus, this article presents the Hellfire Framework, which implements a design space exploration tool based on two basic steps: explore and refine. The tool leads the designer through three main different levels of abstraction: (i) application level; (ii) OS level, and; (iii) hardware architecture level. In the application level, the initial input is a task graph that represents the applications behavior. The resulting application (divided in tasks) uses the OS we provide (and its system calls) to perform varied operations. The OS itself can be mainly configured in terms of real-time scheduling and memory occupation. Finally, the hardware architecture level allows to choose parameters regarding the processor frequency and communication infrastructure. The framework guides the designer through these levels in an explore and refine fashion so that, from a high level description of the application, the entire platform can be assembled with proper design exploration. Results show the exploration and refinement steps in the three levels we propose in different applications for MPSoC-based systems.

Current Techniques and Future Trends in ES's Virtualization

Traditionally, virtualization has been adopted by enterprise industry to make better use of the general purpose processors (single and multicore) besides improving the utilization of existing computational resources, especially in data centers. Until recently, its use in embedded systems (ESs) seemed to be a distant, unnecessary, and unfeasible reality. However, with the rise of each more powerful multiprocessed ESs, typically implemented as multiprocessor system‐on‐chip, virtualization has become a very promising technique to achieve and improve functionalities in future multiprocessor system‐on‐chips. One of the main advantages of virtualizing ESs is to improve the software design quality because legacy software can be reused along with newer applications. Also, we have the classic use cases, such as allowing several operating systems (OSs) to work in the same physical resource, simultaneously. Still, we can provide more secure ESs by splitting the system into user application OS and security certified OS, for instance. Moreover, depending on the way that embedded virtualization is employed, it may be even possible to reduce manufacturing costs and energy consumption levels. However, it is well understood that although ESs deal with increasingly more powerful solutions, they are still far more restricted than general purpose computers, especially in terms of area, memory size, and power consumption. In this article, we provide an extensive analysis of what is being currently offered as embedded virtualization solution, the pros and cons, besides presenting an innovative proposal regarding virtualization for restricted embedded architectures and its possible advantages. Copyright