Fabiano Hessel

Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique

Complex applications implemented as systems on chip (SoC) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP cores and advanced interconnection schemes, such as hierarchical bus architectures or networks on chip (NoC). Modeling applications involves capturing its computation and communication characteristics. Previously proposed communication weighted models (CWM) consider only the application communication aspects. This work proposes a communication dependence and computation model (CDCM) that can simultaneously consider both aspects of an application. It presents a solution to the problem of mapping applications on regular NoC while considering execution time and energy consumption. The use of CDCM is shown to provide estimated average reductions of 40% in execution time, and 20% in energy consumption, for current technologies.

Multilanguage design of heterogeneous systems

Multilanguage solutions are required for the design of heterogeneous systems where different parts belong to different application classes, e.g. control/data or continuous/discrete. The main problem that needs to be solved when dealing with multilanguage design is the refinement of communication between heterogeneous subsystems. This paper discusses the basic concepts of multilanguage design and introduces MUSIC a multilanguage design approach. The paper also shows the application of this approach in the case of a mechatronic system.

From VHDL register transfer level to SystemC transaction level modeling: a comparative case study

Transaction level (TL) modeling is regarded today as the next step in the direction of complex integrated circuits and systems design entry. This means that as this modeling level definition evolves, automated synthesis tools will increasingly support it, allowing design capture to start at a higher abstraction level than today. This work presents a comparison of traditional register transfer level (RTL) modeling and transaction level modeling through the implementation of a simple processor case study. SystemC is a language that naturally supports hardware transaction level descriptions. The R8 processor was described in SystemC TL and RTL versions and these were compared to an equivalent hand-coded VHDL RTL description in some key points, such as simulation efficiency and implementation results. The experiments indicate that TL descriptions present a faster path to system validation and that it is possible to envisage the automation of the design flow from this level of abstraction without significant impact on the quality of the final implementation.

Hardware, software and mechanical cosimulation for automotive applications

The design of automotive systems requires the joint design of hardware, software and micro-mechanical components. In traditional design approaches the different parts are designed by separate groups and the integration of the overall system is made at the final stage. This scheme may induce extra delays and costs because of interfacing problems. The paper presents a new automotive system design approach that offers many advantages including efficient design flow and shorter time to market. The key idea of our approach is to allow for early validation of the overall system through co-simulation. The design starts with a high level specification of each part. In our approach, software is described in C, hardware is described in VHDL and mechanical parts are described in MATLAB. A C-VHDL-MATLAB co-simulation is then used for functional validation of the initial specification. During the design process, the hardware and software parts may be refined using specific techniques and tools. The refinement steps are also validated through co-simulation. In this approach we use two kinds of co-simulation: untimed co-simulation is used for functional validation and timed co-simulation for real time validation. The paper describes the design approach and its successful application to an example from the automotive industry.

Embedded systems' virtualization: The next challenge?

Traditionally, virtualization has been adopted by enterprise industry aiming to make better use of general purpose multi-core processors and its use in embedded systems (ES) seemed to be both a distant and unnecessary reality. However, with the rise of each more powerful multiprocessed ESs, virtualization brings an opportunity to use simultaneously several operating systems (OS) besides offering more secure systems and even an easier way to reuse legacy software. Although ESs have increasingly bigger computational power, they are still far more restricted than general purpose computers, especially in terms of area, memory and power consumption. Therefore, is it possible to use virtualization — a technique that typically demands robust systems — in powerful yet restricted current embedded systems? In this paper we show why the answer should be yes.

RTOS Scheduler Implementation in Hardware and Software for Real Time Applications

In order to enhance performance and improve predictability of the real time systems, implementing some critical operating system functionalities, like time management and task scheduling, in software and others in hardware is an interesting approach. Scheduling decision for real-time embedded software applications is an important problem in real-time operating system (RTOS) and has a great impact on system performance. In this paper, we evaluate the pros and cons of migrating RTOS scheduler implementation from software to hardware. We investigate three different RTOS scheduler implementation approaches: (i) implemented in software running in the same processor of the application tasks, (ii) implemented in software running in a co-processor, and (iii) implemented in hardware, while application tasks are running on a processor. We demonstrate the effectiveness of each approach by simulating and analyzing a set of benchmarks representing different embedded application classes

Hellfire: A design framework for critical embedded systems' applications

Hellfire framework (HellfireFW) presents a design flow for the design of MPSoC based critical embedded systems. Health-care electronics, security equipment and space aircraft are examples of such systems that, besides presenting typical embedded systems constraints, bring new design challenges as their restrictions are even tighter in terms of area, power consumption and high-performance in distributed computing involving real-time processing requirement. In this paper, we present the Hellfire framework, which offers an integrated tool-flow in which design space exploration (DSE), OS customization and static and dynamic application mapping are highly automated. The designer can develop embedded sequential and parallel applications while evaluating how design decisions impact in overall system behavior, in terms of static and dynamic task mapping, performance, deadline miss ratio, communication traffic and energy consumption. Results show that: i) our solution is suitable for hard real-time critical embedded systems, in terms of real-time scheduling and OS overhead; ii) an accurate analysis of critical embedded applications in terms of deadline miss ratio can be done using HellfireFW; iii) designer can better decide which architecture is more suitable for the application; iv) different HW/SW solutions by configuring both the RTOS and the HW platform can be simulated.

Abstract RTOS modeling for embedded systems

Raising the abstraction level is widely seen as a solution to increase productivity, in order to handle the growing complexity of real-time embedded applications and the time-to-market pressures. In this context, the use of a real-time operating system (RTOS) becomes extremely important to the development of applications with real-time systems requirements. However, the use of a detailed RTOS at early design phases is a contra sense, and the existing system level description languages (SLDL) lack support for RTOS modeling at higher abstraction levels. In this paper, we introduce an abstract RTOS model, and a set of refinement steps that allows refining the abstract model to an implementation model at lower abstraction levels. This abstract RTOS model provides the main features available in a typical RTOS, permitting the designer to model parallel and concurrent behavior of real-time embedded applications at higher abstraction levels. We use SystemC language with some extensions to build the abstract RTOS model, allowing a quick evaluation of different scheduling algorithms and synchronization mechanisms at the early stage of system design. An experimental result with a telecom system that consists of fifty tasks with four priority levels shows the usefulness of this model.

The importance of a standard securit y archit ecture for SOA-based iot middleware

The proliferation of the Internet of Things (IoT) in several application domains requires a well-defined infrastructure of systems that provides services for device abstraction and data management, and also supports the development of applications. Middleware for IoT has been recognized as the system that can provide this necessary infrastructure of services and has become increasingly important for IoT in recent years. The architecture of an IoT middleware is usually based on an SOA (service-oriented architecture) standard and has security requirement as one of its main challenges. The large amount of data that flows in this kind of system demands a security architecture that ensures the protection of the entire system. However, none of the existing SOAbased IoT middleware systems have defined a security standard that can be used as a reference architecture. In this sense, this article discusses the importance of defining a standard security architecture for SOA-based IoT middleware, analyzes concepts and existing work, and makes considerations about a set of security services that can be used to define a security architecture to mitigate the security threats in SOA-based IoT middleware systems.

MCI—multilanguage distributed co-simulation tool

Nowadays the design of complex systems requires the cooperation of several teams belonging to different cultures and using different languages. It is necessary to dispose of new design and verification methods to handle multilanguage approaches. This paper presents a multilanguage co-simulation tool that allows co-simulation of multilanguage specifications for complex systems. The main idea of our approach is to allow validation of the functional completeness of the system at a behavioral level. MCI starts with a configuration file that describes the interconnection between modules written in different languages. It generates automatically a software co-simulation bus and the interfaces required to connect the different simulators in a distributed way. The proposed tool is used to assist the design of an adaptive speed control system that was described in three different languages (VHDL, SDL and MatLab).