Sergio Johann Filho

Hellfire: A design framework for critical embedded systems' applications

Hellfire framework (HellfireFW) presents a design flow for the design of MPSoC based critical embedded systems. Health-care electronics, security equipment and space aircraft are examples of such systems that, besides presenting typical embedded systems constraints, bring new design challenges as their restrictions are even tighter in terms of area, power consumption and high-performance in distributed computing involving real-time processing requirement. In this paper, we present the Hellfire framework, which offers an integrated tool-flow in which design space exploration (DSE), OS customization and static and dynamic application mapping are highly automated. The designer can develop embedded sequential and parallel applications while evaluating how design decisions impact in overall system behavior, in terms of static and dynamic task mapping, performance, deadline miss ratio, communication traffic and energy consumption. Results show that: i) our solution is suitable for hard real-time critical embedded systems, in terms of real-time scheduling and OS overhead; ii) an accurate analysis of critical embedded applications in terms of deadline miss ratio can be done using HellfireFW; iii) designer can better decide which architecture is more suitable for the application; iv) different HW/SW solutions by configuring both the RTOS and the HW platform can be simulated.

High-Level Estimation of Execution Time and Energy Consumption for Fast Homogeneous MPSoCs Prototyping

In order to fulfill the increasing performance requirements, complex embedded systems design makes use of many processors communicating through efficient infrastructures, performing multiprocessor-systems-on-chip (MPSoCs). Issues related to execution time and energy consumption estimations become more relevant during the design stage of such systems, in order to verify their compliance with the specification. Different estimation techniques have been proposed, including analytical and simulation-based methods. Analytical methods are faster than simulation-based methods, but the system description is more complex, and sometimes this approach conducts to low precision results misleading future design steps. On the other hand, the more accurate results achieved with simulation-based method, using low-level descriptions, may delay the design making it unfeasible or at least affecting the time-to-market. In this context, improvements in simulation-based methods become pertinent. This paper presents a study, a design flow and a tool for high-level simulation-based estimation of execution time and energy consumption of homogeneous MPSoCs. The implemented tool, which employs the methodology presented in this paper, improved dramatically simulation times when compared to RTL simulations. The preliminary results show that, for some cases, the RTL simulation takes tens hours while the implemented tool gets close estimation results in just few seconds.

Hardware-assisted interrupt delivery optimization for virtualized embedded platforms

Virtualization is already a reality in modern embedded systems. Besides the direct relationship with cost reduction and improved resource utilization, virtualization enables the integration of real-time and general-purpose operating systems and applications on the same hardware platform. The resulting system may inherit deterministic timing characteristics for real-time along with a large software code base for general-purpose operating systems. However, the hypervisor must be carefully designed to take advantage of both types of operating systems. In this paper, we propose an interrupt policy for an embedded hypervisor using hardware-assisted virtualization. Our technique is flexible and can be adopted by applications with different timing constraints. Experimental results show that the interrupt delivery jitter on virtualized systems is close to non-virtualized when the proposed approach is used.

On the design space exploration through the Hellfire Framework

Embedded systems have faced dramatic and extensive changes throughout the past years leading to each more complex designs. Thus, this article presents the Hellfire Framework, which implements a design space exploration tool based on two basic steps: explore and refine. The tool leads the designer through three main different levels of abstraction: (i) application level; (ii) OS level, and; (iii) hardware architecture level. In the application level, the initial input is a task graph that represents the applications behavior. The resulting application (divided in tasks) uses the OS we provide (and its system calls) to perform varied operations. The OS itself can be mainly configured in terms of real-time scheduling and memory occupation. Finally, the hardware architecture level allows to choose parameters regarding the processor frequency and communication infrastructure. The framework guides the designer through these levels in an explore and refine fashion so that, from a high level description of the application, the entire platform can be assembled with proper design exploration. Results show the exploration and refinement steps in the three levels we propose in different applications for MPSoC-based systems.

Embedded cluster-based architecture with high level support - presenting the HC-MPSoC

Multiprocessor System-on-Chip (MPSoC) can be found in almost every market branch and its design typically presents several restrictions such as chip area and energy consumption. State-of-art MPSoCs uses networks-on-chip as the primary communication infrastructure and the tendency is that NoC-based systems will still be used for a long time, thanks to a greater design flexibility and also a high communication bandwidth and parallelism. However, such systems also have certain usage restrictions, such as the location of the tasks that compose the application. Mapping and partitioning techniques seek to solve this problem or at least reduce it to a non critical point by diving tasks along the architecture but are not always completely successful. In this context, cluster-based architectures emerges as a viable alternative to MPSoCs. This type of system typically has a hybrid architecture on its constitution, using more than one communication infrastructure, thus being able to group elements by affinity and still use high-speed communication channels, such as NoCs. In this way, the presented work introduces the HC-MPSoC, an architecture for cluster-based intrachip systems, which uses buses and a NoC in a joint way, forming groups of elements independently distributed throughout the platform. The extensions made on the HellfireOS in order to execute it over the hybrid architecture are also presented. All HC-MPSoC modules as well as the HellfireOS modules and the results obtained using the platform are presented along the text.

NoC-based platform for embedded software design: An extension of the Hellfire Framework

This paper presents an extension of the Hellfire Framework (HFFW), providing an intuitive and powerful web interface to build, test and debug a complete Multiprocessor System-on-Chip (MPSoC). Among the new functionalities presented, it is possible to highlight: i) the architecture builder tool, used to set up all the MPSoC architecture; ii) the possibility to use a Network-on-Chip (NoC) as the communication mean, and; iii) a new simulator, providing a fast and accurate high level Instructions Set Simulator (ISS) with a miss ratio less than 5%. In order to validate the new simulator accuracy several tests were taken, first using traffic generators and then an implementation of the Secure Hash Algorithm (SHA). The achieved results are discussed throughout the paper.

An RTOS Methodology for NoC Based Systems' Support -- The HellfireOS Case Study

Modern multi-processor systems-on-a-chip currently count on computational resources previously only seen on general purpose machines. Each more, the evolution on the manufacturing process allows more features to be included on these embedded systems and determine an increased complexity of their hardware and software design. This increase of design complexity requires tools that may reduce the time spent on the development process of several parts that compose these systems. In the final design stages, the application and its properties are represented by tasks and processors managed by an operating system, so a well defined API can be used by developers to explore MPSoCs computational resources in a fast manner. This work presents a case study of applications running on top of Hellfire OS, and how real-time properties are modeled on the operating system. Different scenarios are presented on the results, involving RTOS performance for common system calls, message passing performance for communicating tasks a dynamic reconfiguration of real-time task sets using load balancing techniques.

Design and analysis of the HF-RISC processor targeting voltage scaling applications

This paper presents the design and analysis of HF-RISC, a 32-bit RISC processor, targeting voltage scaling applications. We start proposing a design flow that enables the processor to operate at multiple voltage levels and explore how this flow enables designers to leverage the advantages of low voltage designs. Next, we present a set of case study designs of HF-RISC in a 28nm FD-SOI technology assessing their area, performance and power figures. Using the collected data we discuss how our flow can enable better design space exploration for voltage scaling applications and define guidelines for achieving lower power and better power efficiency. Accordingly, the obtained results indicate that the proposed flow allows 9.5% lower power overall and 25.5% better energy efficiency in HF-RISC design.

A VHDL based approach for fast and accurate energy consumption estimations

Efficient energy consumption became an important requirement and constraint to be considered in many systems implementations, mainly to the embedded ones. Accurate and efficient power estimation during the design phase is required, in order to meet the power specifications without a costly redesign. High abstraction levels descriptions enable fast energy consumption estimations, but hardly enable accurate estimations. It normally requires evaluations at low abstraction levels, such as electric ones. On the other hand, low abstraction levels require too much design effort and design time. In this sense, this work presents an approach for energy consumption estimation for systems written in synthesizable VHDLs. A VHDL cell library is the base of the methodology, which is characterized with some relevant energy consumption information according to foundry parameters. The use of this approach leads to high-quality energy consumption estimations and design time saving.