Alexandra L. Zimpeck

Impact of gate workfunction fluctuation on FinFET standard cells

FinFET technology is pointed as the main candidate to replace CMOS bulk process in sub-22nm circuits. Predictive technology and design exploration help to understand major effects of variability sources and their impact on circuit performance and power consumption. In this sense, new design methodologies and new EDA tools must be able to deal with the new fabrication process and variability challenges. This paper presents a predictive evaluation of the impact of workfunction variation in the timing and power of standard cells in FinFETs future technology nodes.

FinFET cells with different transistor sizing techniques against PVT variations

This paper investigates the impact of the main sources of variation on performance and power consumption for different transistor sizing techniques applied to cells in FinFET technologies. The analysis considers process, voltage and temperature variations, individually. Voltage and temperature variations are combined to obtain an insight into their contributions. Results are useful to define the variability contributions in the early design steps and to select the most appropriate transistor sizing technique for a targeted application. Results provide a quantitative understanding of each contribution considering a 14nm FinFET technology.

Evaluating the Impact of Environment and Physical Variability on the I ON Current of 20nm FinFET Devices

This paper presents an evaluation of process and temperature variability in PFET and NFET transistors using predictive 20nm FinFET technologies. The objective of this work is to evaluate the environment and physical variability impact in FinFET devices. The main physical parameters affected by process variability are fin width, fin height, gate length, metal gate workfunction and oxide thickness. Monte Carlo analysis shows high dependence of the workfunction fluctuations on the device behaviour. This work also evaluates the environment variability, investigating the influence of temperature variations. The main goal is to highlight the influence of these variations in the ION current for predictive FinFET technologies.

Impact of variability effects on FinFET transistors and combinational cells

This work provides a predictive evaluation of PVT variability impact on sub-22nm FinFET devices and a set of combinational cells. Results show that metal gate workfunction fluctuation is the main source of process variability, severely affecting the OFF current especially on NFET devices. Combinational cells suffer from temperature impact on the power consumption and also from voltage drop that increases more than three times the timing results of the majority of cells.

Permanent and single event transient faults reliability evaluation EDA tool

Abstract In nanotechnology domain, reliability is a fundamental concern in the design and manufacturing process of VLSI circuits. Thus, this paper presents a tool developed to evaluate the reliability of logic cells in order to provide a set of information to improve design robustness. The tool is able to evaluate logic cells under Single Event Transient (SET) faults and, also, permanent faults such as Stuck-On (SOnF) and Stuck-Open (SOF). The information produced by this tool help designers to choose the most reliable cells to be adopted in their designs.

Process variability in FinFET standard cells with different transistor sizing techniques

This work evaluates the impact of process variations on the electrical behavior of a set of combinational cells considering different transistor sizing techniques: minimum sizing, logical effort and delay-optimized sizing. The optimization is done by a transistor sizing tool that employs geometric programming. The main point is to observe how transistor sizing techniques could be explored for the FinFET standard cells design. Results show that cells sized accordingly logical effort technique are more sensible to process variability when compared with minimum transistor sizing. The best process variability robustness is achieved by adopting the delay-optimized sizing technique.

Impact of different transistor arrangements on gate variability

This paper evaluates a set of complex cells with different transistor arrangements that implement the same logic function. These cells were evaluated under nominal conditions and with gate variability at layout level. The purpose is to verify what topology is more appropriate to increase the robustness of cells regarding the process variability issues. Results emphasize the importance of investigating the effects caused by process variability in FinFET technologies, as the electrical characteristics of circuits suffer significant changes. In general, the best choice is to use the network that the transistor in series is as far as possible to the output node. However, a trade-off needs to be done due to performance and power consumption penalties.

Evaluation of variability using Schmitt trigger on full adders layout

Abstract The aggressive technology and voltage scaling which modern digital circuits are facing introduce a higher influence in metrics, as performance and power consumption, due to process variability. To mitigate that, novel techniques are proposed and tested in the literature. This work analyzes the impact on variability robustness using a technique based on the replacement of full adders internal inverters by Schmitt Triggers. Some works point that the given technique helps to improve the variability robustness at the electrical level. Therefore, analysis has been performed at layout level using the 7 nm FinFET technology node from ASAP7 library and the technique was applied on four full adder designs. Performance, energy and area are taken into account. Results show up to 64.74% and 66.6% improvement in average delay and energy variability robustness, respectively.

Robustness of Sub-22nm multigate devices against physical variability

This work provides a detailed set of predictive data about FinFET and Trigate devices behavior considering process variability effects in ON and OFF currents. These evaluations help to understand the impact of variability sources identifying relevant behavior standards with respect to the use of FinFET and Trigate devices. The IOFF suffers the higher impact of geometric variability, mainly on FinFET devices. PFET devices and the LSTP model are also more sensitive than NFET devices and high performance models. Results highlights that Trigate devices are up to 10% less sensitive to gate length variations.

Robustness evaluation of finFET transistors under PVT variability

This work provides a predictive evaluation of the impact that PVT variability causes on ON and OFF currents of FinFET transistors in technologies sub-22nm. Results show that the OFF current is the most impacted by all sources of variability. In terms of process variability effects, the LG and WFF variations cause the worst values to IOFF, especially for PFET and NFET devices, respectively. Voltage and temperature variations effects damage more the PFET devices.