Fernanda Lima Kastensmidt

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

Triple modular redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets in the routing from provoking undesirable connections between signals from distinct redundant logic parts, which can generate an error in the output. This paper investigates the optimal design of the TMR logic (e.g., by cleverly inserting voters) to ensure robustness. Four different versions of a TMR digital filter were analyzed by fault injection. Faults were randomly inserted straight into the bitstream of the FPGA. The experimental results presented in this paper demonstrate that the number and placement of voters in the TMR design can directly affect the fault tolerance, ranging from 4.03% to 0.98% the number of upsets in the routing able to cause an error in the TMR circuit.

Physical design methodologies for performance predictability and manufacturability

The Physical Design Methodology of Integrated Systems is increasing its relevance in deep submicron technologies due to the appearance of new problems related to electrical behavior and performance predictability. This paper presents some techniques to improve reliability and manufacturability by the use of some layout strategies. One main approach is the search of regular solutions as the use of a layout composed by a matrix of cells. It is discussed the effects of layout strategies in the design of reconfigurable systems.

Using Bulk Built-in Current Sensors to Detect Soft Errors

Connecting a built-in current sensor in the design bulk of a digital system increases sensitivity for detecting transient upsets in combinational and sequential logic. SPICE simulations validate this approach and show only minor penalties in terms of area, performance, and power consumption

A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip

A novel strategy to detect interconnect faults between distinct channels in networks-on-chip is proposed. Short faults between distinct channels in the data, control and communication handshake lines are considered in a cost-effective test sequence for Mesh NoC topologies based on XY routing.

Single Event Transients in Logic Circuits—Load and Propagation Induced Pulse Broadening

The generation and propagation of single event transients (SET) in logic gate chains is studied and modeled. Regarding SET generation, we investigate the dependence of the generated SET pulse width on the struck node capacitance. Rising node capacitance may lead to amplified pulse width, indicating that increasing load capacitance alone is not an option for radiation hardening. SET propagation in logic chains is also studied, and it is shown that significant broadening or attenuation of the propagated transient pulse width may be observed. It is shown that the chain design (propagation delay of high to low and low to high transitions) has a major impact on broadening or attenuation of the propagated transient pulse. For the first time a suitable model for SET broadening is provided.

Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk

As the technology scales down into deep sub-micron domain, more IP cores are integrated in the same die and new communication architectures are used to meet performance and power constraints. However, the same technologic advance makes devices and interconnects more sensitive to new types of malfunctions and failures, such as crosstalk and transient faults. This paper proposes fault tolerant techniques to protect NoC routers against the occurrence of soft errors and crosstalk at the same time, with minimum area and performance overhead. Experimental results show that a cost-effective protection alternative can be achieved by the combination of error correction codes and time redundancy techniques

Analyzing the Impact of Single-Event-Induced Charge Sharing in Complex Circuits

This paper proposes a soft error characterization methodology to analyze multiple faults caused by single-event-induced charge sharing in standard-cell based ASIC designs. Fault injection campaigns have been executed using data provided by placement analysis as well as a pulse width modeling through electrical simulation. Experimental results demonstrate that the error rate can be largely overestimated if placement is not considered.

Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults

We propose a fault tolerance method for torus NoCs capable of increase the yield with minimal performance overhead. The proposed approach consists in detecting and diagnosing interconnect faults using BIST structures and activating alternative paths for the faulty links. Experimental results show that alternative fault-free paths are found by the dynamic routing for 95% of the diagnosed faults (stuck-at and pairwise shorts within a single link or between any two links).

Designing and testing fault-tolerant techniques for SRAM-based FPGAs

This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable architecture, or they can be implemented at the high-level description, without modification in the FPGA architecture. The high-level method presented in this work is based on Triple Modular Redundancy (TMR) and a combination of Duplication Modular Redundancy (DMR) with Concurrent Error Detection (CED) techniques, which are able to cope with upsets in the combinational and in the sequential logic. The methodology was validated by fault injection experiments in an emulation board. Results have been analyzed in terms of reliability, input and output pin count, area and power dissipation.

Synchronizing triple modular redundant designs in dynamic partial reconfiguration applications

This paper presents an innovative method that allows the use of dynamic partial reconfiguration combined with triple modular redundancy (TMR) in SRAM-based FPGAs fault-tolerant designs. The method uses large grain TMR with special voters capable of signalizing the faulty module, and check point states that allow the sequential synchronization of the recovered module. As a result, only the faulty domain is reconfigured, minimizing time and energy spent in the process. In addition, the use of check-point states avoids system downtime, since the synchronization of the recovered module is performed while the others are kept running. Experimental results show that the method has a reduced fault recovery time compared to the standard TMR implementation, maintaining the compatible area overhead and performance.