Alexandre Verle

Circuit sizing method under delay constraint

In the last step of the design flow, circuit performance optimization is a difficult task to realize. The goal of this work is to avoid the use of CPU time expensive random mathematical methods, by defining an accurate and deterministic circuit sizing protocol, allowing easy and fast sizing of circuits at the required speed. We propose a coefficient based approach to solve the divergence branch problem for circuit sizing. Validation is given by comparing, in a standard 180nm CMOS process, the performance of different ISCAS benchmarks sized with an industrial tool and following our methodology

Speed indicators for circuit optimization

Due to the development of high performance portable applications associated to the high-density integration allowed by deep submicron processes, circuit optimization under delay constraints has emerged as a critical issue for VLSI designers. The objective of this work is to avoid the use of random mathematical methods (very CPU time expensive), by defining simple, fast and deterministic indicators allowing easy and fast implementation of circuits at the required speed. We propose to extend the method of equal sensitivity, previously developed for combinatorial paths [1], to circuit sizing in order to solve the circuit convergence branch problem. We propose a coefficient based approach to solve the divergence branch problem. Validation is given by comparing with an industrial tool the performance of different benchmarks implemented in a standard 180nm CMOS process.

Circuit optimization based on speed indicators

This paper addresses the problem of circuit performance optimization that is a complete task to realize in the last step of the I.C. design flow. The goal of this work is to avoid the use of random mathematical methods (very CPU time expensive), by defining simple, fast and deterministic indicators allowing easy and fast implementation of circuits at the required speed. We propose to extend the method of equal sensitivity, previously developed for combinatorial paths, to combinatorial circuit sizing in order to solve the convergence branch problem. We also propose a coefficient based approach to solve the divergence branch problem. Validations are given by comparing the performance of different benchmarks obtained with our protocol and with an industrial tool in a standard 180 nm CMOS process.

Performance Metric Based Optimization Protocol

Optimizing digital designs implies a selection of circuit implementation based on different cost criteria. Post-processing methods such as transistor sizing, buffer insertion or logic transformation can be used for optimizing critical paths to satisfy timing constraints. However most optimization tools are not able to select between the different optimization alternatives and have high CPU execution time.

Delay bound based CMOS gate sizing technique

In this paper we address the problem of delay constraint distribution on CMOS combinatorial paths. We first define a way to determine on any path the reasonable bounds of delay characterizing the structure. Then we define two constraint distribution methods that we compare to the equal delay distribution and to an industrial tool based on Newton-Raphson like algorithms. Validation is obtained on a 0.25 /spl mu/m process by comparing the different constraint distribution techniques on various benchmarks.

CMOS Gate Sizing under Delay Constraint

In this paper we address the problem of delay constraint distribution on a CMOS combinatorial path. We first define a way to determine on any path the reasonable bounds of delay characterizing the structure. Then we define two constraint distribution methods that we compare to the equal delay distribution and to an industrial tool based on the Newton-Raphson like algorithm. Validation is obtained on a 0.25μm process by comparing the different constraint distribution techniques on various benchmarks.

Metric definition for circuit speed optimization

Designing high performance circuits requires the definition of trade-off between speed, power and area. Based on a design oriented modeling of the delay, this work presents a method for defining metrics for load criticality analysis of different nodes. The purpose of this work is to define indicators for the selection of optimization alternatives. The validation of these indicators is obtained through comparison to the critical loads determined from Spice simulations. The application to various benchmarks shows that, without enumeration, an initial path delay improvement can be obtained at reduced area/power cost by just applying this metric to identify the critical nodes that are the best candidates for speed optimization.