Daniel Auvergne

Signal transition time effect on CMOS delay evaluation

Realistic modeling of gate delay is of great importance in evaluating circuit path performances. Nonzero signal rise and fall times contribute to gate propagation delays and must be considered for realistic characterization of standard cells. In this paper, we present an accurate and simple method to model output rise and fall times. We show that this can be obtained in a framework of a more general macromodel of delays, using step responses corrected for slow-input ramp duration effects. The concept of fast and slow transitions is clearly explained in terms of the drive current available in the structure. A first validation of this modeling has been obtained by comparing calculated inverter output-ramp duration to simulated ones (HSPICE level and foundry card model on 0.35-/spl mu/m and 0.25-/spl mu/m processes). Finally, both the delay and output-ramp modeling are validated by comparing inverter array calculated and simulated total delay values.

Design and selection of buffers for minimum power-delay product

Using explicit modeling of delays, we present and discuss real design conditions of CMOS buffers from the viewpoint of power dissipation. Efficiency of buffer implementation is first studied through the definition of limit for buffer insertion. Closed form alternatives to the design for minimum power-delay product are then proposed in terms of this limit. Validations are obtained through SPICE simulations on two stage inverter arrays. Applications are given to a standard cell library in comparing implementations for different selection alternatives.

Explicit evaluation of short circuit power dissipation for CMOS logic structures

For supply voltage standards such as Vdd > V TN + |V TP | short-circuit power dissipation significantly contributes to the total power dissipation in ICs. We propose a new alternative for the estimation of the short-circuit power dissipation, Psc, in CMOS structures. A first order calculation results in an explicit formulation for Psc, which clearly shows up the design and load parameters. Validations are performed on different configurations of inverters by comparison with HSPICE simulations. Discussions on the relative importance of short-circuit and dynamic power dissipation is given, together with considerations allowing an easy extension to gates.

A Virtual CMOS Library Approach for East Layout Synthesis

We present a layout synthesis methodology based on the use of virtual CMOS libraries, i.e. using no pre-characterized cells. The proposed methodology is organized around an automatic layout generator, allowing fast on-the-fly implementation of macro-cells. The generator eliminates the need for post-layout compaction procedures and in addition produces parasitic capacitances estimations. Results show that it is possible to quickly generate dense layouts, allowing fast prototyping of logic functions. The proposed method can change the way layout synthesis is seen today, since accurate parasitic evaluation is an important prerequisite for optimized submicronic designs.

Temperature effect on delay for low voltage applications [CMOS ICs]

This paper presents one of the first analysis of the temperature dependence of CMOS integrated circuit delay at low voltage. Based on a low voltage extended Sakurais /spl alpha/-power current law, a detail analysis of the temperature and voltage sensitivity of CMOS structure delay is given. Coupling effects between temperature and voltage are clearly demonstrated. Specific derating factors are defined for the low voltage range (1-3 V/sub TO/). Experimental validations are obtained on specific ring oscillators integrated on a 0.7 /spl mu/m process by comparing the temperature and voltage evolution of the measured oscillation period to the calculated ones. A low temperature sensitivity operating region has been clearly identified and appears in excellent agreement with the expected calculated values.

Power and delay macro-modeling for submicronic CMOS process: application to low power design

Abstract Designing in the deep submicronic range implies to manage trade off between speed and power. This paper presents an improved macro model for the delay and power dissipation of CMOS structures. This model is based on a simple but realistic MOS model to include the carrier velocity saturation effect of submicronic MOSFETs, the input-to-output coupling capacitance and the short circuit effects. These effects are responsible of the non-linear relationship between the inverter real delay and the input ramp rise or fall time. A complete representation is obtained in analytical equations of the delay and the power dissipation which give performance values in excellent agreement if compared to simulated ones (SPICE level 6). This has been validated on a .65 micron process, using the complete foundry specification for a large extent of input slope configurations ( τ IN t HLS = 1–20 ) and inverter internal configuration ratios. Applications are given to temperature effects in low voltage designs, low power buffer design and to standard cell performance characterization.

Delay modelling improvement for low voltage applications

Based on an explicit formulation of delays, an improved model for low voltage operation of CMOS inverter has been derived. Extrinsic and intrinsic effects, such as transistor current variation, input slew rate effects and mobility improvement at low field are considered. Explicit dependence of inverter delay on input controlling ramp is given with clear evidence of supply and threshold voltage influences. Validations are obtained by comparing the calculated and measured oscillation period evolution of ring oscillators, under supply voltage conditions varying from standard 5/spl nu/, to values as low as the highest threshold voltage of the process involved. The speed performance evolution and the limits to the reduction of supply voltage are clearly given in terms of threshold voltage values.

Internal power modelling and minimization in CMOS inverters

We present in this paper an alternative for the internal (short-circuit and overshoot) power dissipation estimation of CMOS structures. Using a first order macro-modelling, we consider submicronic additional effects such as: input slow dependency of short-circuit currents and input-to-output coupling. Considering an equivalent capacitance concept we directly compare the different power components. Validations are presented by comparing simulated values (HSPICE level 6, foundry model 0.7 /spl mu/m) to calculated ones. Application to buffer design enlightens the importance of the internal power component and clearly shows that common sizing alternatives for power and delay minimization can be considered.

Design Optimization with Automated Cell Generation

It is well recognized that designs based on automated standard cell flow have been found slower and larger in area than comparable designs manually generated or optimized. On the other hand it becomes necessary for designers to quickly prototype IP blocks in newly available processes. This paper describes an approach combining a performance optimization by path classification (POPS) tool with a transistor level layout synthesis tool (I2P2) dedicated to CMOS synchronous design fast generation. Validations are given on a 0.18 μm CMOS process by comparing standard cell approach to the proposed approach.

Transistor Level Synthesis Dedicated to Fast I.P. Prototyping

Standard cell libraries have been successfully used for years, however with the emergence of new technologies and the increasing complexity of designs, this concept becomes less and less attractive. Most of the time, cells are too generic and not well suited to the block being created. As a result the final design is not well optimized in terms of timing, power and area.This paper describes a new approach based on transistor level layout synthesis for CMOS IP cores rapid prototyping (~100k transistors).