Alexei Sadovnikov

Impact of reverse EB stress and mixed-mode stress on low-frequency noise for SiGe HBTs in forward and inverse modes

We present in this work the impact of electrical reliability stress on low-frequency noise for SiGe HBTs in forward and inverse modes. The reverse EB stress and the forward mixed-mode stress are investigated. For the first time inverse mode noise is used as a tool to investigate stress-induced damage. The fact that reverse EB stress degrades SiGe HBTs low-frequency noise in the forward mode but not in the inverse mode indicates that the stress-induced traps are located in the EB spacer oxide. Mixed-mode stress degrades both the forward and inverse modes low-frequency noise, consistent with the theory that both the EB and CB junctions are damaged during the stress. The observed noise degradation under stress calls for accurate noise aging modeling in reliability simulation.

Considerations for forward active mode reliability in an advanced hetero-junction bipolar transistor

The implementation of safe operating area (SOA) is discussed in this paper to quantify electrical, thermal, and Hot Carrier (HC) limits for a SiGe hetero-junction bipolar transistor (HBT) in a forward active mode. An electrical limit should be constructed to prevent an unexpected catastrophic failure at a circuit level considering impedance to the base node of HBTs simultaneously affected by current and voltage, unlike an individual HBT measured by parameter analyzers. Also, an investigation of the critical parameter degradation such as Beta is observed in a full range of active mode, calculating the maximum tolerable current, bias, and power relative to the performance of a HBT. We demonstrate the unique behavior of current dependence of Beta degradation by a simulation of impact ionization location and rate, accompanied by Kirk effect. In addition, we associate a 1/VBC model for time-to-fail (TTF) extrapolated into the use condition compared to a conventional VBC model.

Stacked Contact Electromigration in advanced SiGe heterojunction bipolar transistors

Contact Electromigration (EM) constraining the performance for a SiGe hetero-junction bipolar transistor (HBT) is investigated. By incorporating a stacked contact structure with Via, the time-to-fail (TTF) increases by ten-fold and contact EM current density (JC_CNT_EM) increases by three-fold. These improvements are shown in experiments incorporating a space between contact and Via, a multi-level stack, and multi-Via stack effects. Also this result can be theoretically explained by a restoring force between contact and Via called Blech effect and unidirectional current flow. Consequently, JC_CNT_EM is no longer limited in a safe operating area (SOA) of a HBT and EM is regulated by only the top metal in a stacked contact structure. This allows us to design an EM enhanced HBT primitive cell without compromising device performance and to eliminate processing problems caused by rectangular contact.