Alexey Vert

GaAs on Si epitaxy by aspect ratio trapping: analysis and reduction of defects propagating along the trench direction

The Aspect Ratio Trapping technique has been extensively evaluated for improving the quality of III-V heteroepitaxial films grown on Si, due to the potential for terminating defects at the sidewalls of SiO2 patterned trenches that enclose the growth region. However, defects propagating along the trench direction cannot be effectively confined with this technique. We studied the effect of the trench bottom geometry on the density of defects of GaAs fins, grown by metal-organic chemical vapor deposition on 300 mm Si (001) wafers inside narrow (<90 nm wide) trenches. Plan view and cross sectional Scanning Electron Microscopy and Transmission Electron Microscopy, together with High Resolution X-Ray Diffraction, were used to evaluate the crystal quality of GaAs. The prevalent defects that reach the top surface of GaAs fins are {111} twin planes propagating along the trench direction. The lowest density of twin planes, ∼8 × 108 cm−2, was achieved on “V” shaped bottom trenches, where GaAs nucleation occurs only ...

Epitaxial growth of GaSb and InAs fins on 300 mm Si (001) by aspect ratio trapping

We report on the monolithic integration of GaSb and InAs fins on on-axis 300 mm Si (001) by metal-organic chemical vapor deposition. The thickness of the GaAs/Si (001) fins used as a template is optimized to allow the formation of {111} facets and the confinement of defects generated at the GaAs/GaSb and GaAs/InAs interfaces by means of the aspect ratio trapping technique. Anti-phase domains are avoided via a careful design of the GaAs/Si interface. Threading dislocations in GaSb are controlled through the formation of an interfacial misfit dislocation array along the GaSb/GaAs [1¯11] and [11¯1] interfaces. Defects on InAs are controlled through the promotion of a two-dimensional growth, which spontaneously occurs on GaAs {111} planes. The results represent a step forward towards the integration of III–V nano-scale photonic and electronic components on a Si complementary metal-oxide-semiconductor compatible platform using a precisely engineered GaAs on Si template.

Backside and edge cleaning of III–V on Si wafers for contamination free manufacturing

III-V on Silicon epitaxial wafers are typically contaminated with residual III-V materials on the backside, bevel and front side exclusion zone. This contamination poses a risk for device manufacturing. The level of contamination can vary from trace to gross, depending on the epitaxial deposition process and method of backside wafer surface protection. Even when the backside surface is well protected and cleaned, trace amounts of III-V material including arsenic can still be detected. Wet clean methods usually use acid chemistries and if not optimized may involve significant chemical cost, safety risks, and contamination issues. Wafer backside and edge cleaning processes, employed to remove residual III-V material need to be designed for robust performance with a wide range of deposited materials and repeatable results in order to ensure contamination free manufacturing at subsequent steps of the fabrication flow.

Growth of low defect-density InP on exact Si (001) substrates by metalorganic chemical vapor deposition with position-controlled seed arrays

Growth of InP with high crystalline quality on exact Si (001) substrates is reported. InP seed arrays were deposited in 30 nm-wide SiO2 trenches along the [1 -1 0] direction on Si substrates. Coalesced InP films were regrown on the seed layer arrays after removal of the SiO2 mask. Cross-sectional transmission electron microscopy shows anisotropic distribution of defects along the [1 1 0] and [1 -1 0] directions. From x-ray diffraction measurement, full-width-at-half-maximum as small as 78 arcsec has been achieved from 2.3 μm InP in a coupled ω/2θ scan.