Saikumar Vivekanand

GaAs on Si epitaxy by aspect ratio trapping: analysis and reduction of defects propagating along the trench direction

The Aspect Ratio Trapping technique has been extensively evaluated for improving the quality of III-V heteroepitaxial films grown on Si, due to the potential for terminating defects at the sidewalls of SiO2 patterned trenches that enclose the growth region. However, defects propagating along the trench direction cannot be effectively confined with this technique. We studied the effect of the trench bottom geometry on the density of defects of GaAs fins, grown by metal-organic chemical vapor deposition on 300 mm Si (001) wafers inside narrow (<90 nm wide) trenches. Plan view and cross sectional Scanning Electron Microscopy and Transmission Electron Microscopy, together with High Resolution X-Ray Diffraction, were used to evaluate the crystal quality of GaAs. The prevalent defects that reach the top surface of GaAs fins are {111} twin planes propagating along the trench direction. The lowest density of twin planes, ∼8 × 108 cm−2, was achieved on “V” shaped bottom trenches, where GaAs nucleation occurs only ...

STLM: A Sidewall TLM Structure for Accurate Extraction of Ultralow Specific Contact Resistivity

We propose a very large scale integration compatible, modified transfer length method (TLM) structure, called sidewall TLM, to minimize the effect of spreading resistance and thus improving the resolution of the TLM method. This is achieved by allowing uniform current collection perpendicularly through the sidewall of the contact. We demonstrate statistically significant specific contact resistivity (ρ_c) extraction of 2×10^-8Ω cm² and 5×10^-9Ω cm² for n-type and p-type NiSi contacts, respectively, on a 300-mm wafer, which are about 50% less than those extracted using the conventional TLM structure. The proposed structure also shows a tighter distribution in the extracted ρ_c values. The results show the importance of such test structures to accurately extract ultralow ρ_c values relevant to sub-14-nm technology nodes.

Epitaxial growth of GaSb and InAs fins on 300 mm Si (001) by aspect ratio trapping

We report on the monolithic integration of GaSb and InAs fins on on-axis 300 mm Si (001) by metal-organic chemical vapor deposition. The thickness of the GaAs/Si (001) fins used as a template is optimized to allow the formation of {111} facets and the confinement of defects generated at the GaAs/GaSb and GaAs/InAs interfaces by means of the aspect ratio trapping technique. Anti-phase domains are avoided via a careful design of the GaAs/Si interface. Threading dislocations in GaSb are controlled through the formation of an interfacial misfit dislocation array along the GaSb/GaAs [1¯11] and [11¯1] interfaces. Defects on InAs are controlled through the promotion of a two-dimensional growth, which spontaneously occurs on GaAs {111} planes. The results represent a step forward towards the integration of III–V nano-scale photonic and electronic components on a Si complementary metal-oxide-semiconductor compatible platform using a precisely engineered GaAs on Si template.

Contact resistance improvement by dielectric breakdown in semiconductor-dielectric-metal contact

We propose an approach for reduction of the contact resistance by inducing dielectric breakdown in a Si-dielectric-metal contact stack. We observe a 36% reduction in the contact resistance as well as an improvement in the uniformity in the distribution after dielectric breakdown. The results open up interesting device applications in complementary metal oxide semiconductor technology.

Backside and edge cleaning of III–V on Si wafers for contamination free manufacturing

III-V on Silicon epitaxial wafers are typically contaminated with residual III-V materials on the backside, bevel and front side exclusion zone. This contamination poses a risk for device manufacturing. The level of contamination can vary from trace to gross, depending on the epitaxial deposition process and method of backside wafer surface protection. Even when the backside surface is well protected and cleaned, trace amounts of III-V material including arsenic can still be detected. Wet clean methods usually use acid chemistries and if not optimized may involve significant chemical cost, safety risks, and contamination issues. Wafer backside and edge cleaning processes, employed to remove residual III-V material need to be designed for robust performance with a wide range of deposited materials and repeatable results in order to ensure contamination free manufacturing at subsequent steps of the fabrication flow.

Application of cluster Ion (carbon) implantation for strain applications

For 28nm and beyond technology nodes it is essential to enhance carrier mobility of the devices by introducing embedded Si:C structures using new materials or structures or new implant and anneal process schemes. In this article we review and verify available information using Si:C formation through implant and anneal approach with low temperature cluster carbon and cluster phosphorous implants. We show here the difference in process results for single and double carbon implants for various pre-anneal and laser annealing conditions. This article explores the effect of cluster carbon implants on various pre-anneal conditions and implant temperature effects on sheet resistance, carbon substitution and junction depths which are critical in determining important device characteristics.

Strained Si:C using low temperature clustercarbon implants and laser annealing

It is shown that Cluster Carbon implantation can be an effective process for making Si:C stressor layer, particularly due to the self-amorphization feature of cluster implantation. Carbon incorporation challenges the formation of NMOS junction structures due to the competition between carbon and dopant atoms to occupy the Si lattice sites and also excess carbon causes serious deactivation of the dopant species. This work now extends to show the effect of low temperature multiple carbon implants and laser annealing on sheet resistance (Rs), carbon substituitionality ([C]subs) and re-crystallization of Si:C layer. The results show that sheet resistance is lower for room temperature implants when compared to cold implants for any anneal condition and but the carbon substitution is slightly higher at low temperature cases. Good recrystallization with no visible defects as seen through XTEM images were observed for both RT and cold implant cases for spike annealed cases. For low temperature RTA anneals, cold i...