Ali Alaeldine

Investigation on ESD Transient Immunity of Integrated Circuits

This paper presents a measurement methodology aimed at predicting the susceptibility of integrated circuits against electrostatic discharge (ESD) stresses. In our application, a very fast transmission line pulsing (VF-TLP) test bench is used to inject a disturbance into an IC under operation. For simulation purposes, each part of the test bench is modeled separately, and these models are assembled in order to obtain a complete model representing both the injection set-up and the IC itself. The suggested injection model is validated thanks to correlations between measurements and simulations on a full- custom 0.18 mum CMOS IC.

Efficiency of Embedded On-Chip EMI Protections to Continuous Harmonic and Fast Transient Pulses with Respect to Substrate Injection

This paper presents a comparative study of the efficiency of several embedded EMI protections for integrated circuits (ICs) with respect to direct power injection (DPI) and very fast transmission-line pulsing (VF-TLP) into the substrate of the IC. This study involves three functionally identical cores, differing only by their EMI protection strategies (RC protection, isolated substrate, meshed power supply network) which were initially designed for low-emission design guidelines. Through extensive measurements, a classification between these strategies is established for both injection methods, leading to the introduction of design guidelines for the minimization of conducted susceptibility to substrate injection.

Comparison among emission and susceptibility reduction techniques for electromagnetic interference in digital integrated circuits

This paper presents a comparative study of susceptibility reduction techniques for electromagnetic interference (EMI) in digital integrated circuits (ICs). Both direct power injection (DPI) and very-fast transmission-line pulsing (VF-TLP) methods are used to inject interference into the substrate of a single test chip. This IC is built around six functionally identical cores, differing only by their EMI protection strategies (RC protection, isolated substrate, meshed power supply network) which were initially designed for low emission design rules. The ranking of three of these cores in terms of electromagnetic immunity is then compared with the one of their radiated emission, thanks to near-field scanning (NFS) measurements. This leads to the establishing of design guidelines for low EMI in digital ICs.

Assessment of the Immunity of Unshielded Multi-Core Integrated Circuits to Near-Field Injection

This paper presents a comparative assessment of the electromagnetic immunity of 4 integrated logic cores to near-field injection. These cores, located on the same die, are identical from a functional point of view, but differ by their design strategies. The injection is performed above each core according to the 6 components of the electromagnetic field, using appropriate probes. These results demonstrate that the die and bondwires of an integrated circuit can be sensitive to both magnetic and electric fields, and that some design rules can improve the immunity of integrated circuits to near-field interference.

Predicting the immunity of integrated circuits through measurement methods and simulation models

This paper introduces complete simulation models of typical electromagnetic immunity tests for integrated circuits (ICs). Direct Power Injection (DPI), Near-field (NF) and Very- Fast Transmission Line Pulsing (VF-TLP) experiments are modeled accurately, and comparisons between simulations and measurements for each set-up demonstrate the validity of this approach and lead to the development of an immunity prediction method for ICs.

A comprehensive simulation model for immunity prediction in integrated circuits with respect to substrate injection

This paper presents a comprehensive modelling methodology for the electromagnetic immunity of integrated circuits (ICs) to direct power injection (DPI). The aim of this study is to predict the susceptibility of ICs by the means of simulations performed on an appropriate electrical model of different integrated logic cores located in the same die. These cores are identical from a functional point of view, but differ by their design strategies. The simulation model includes the whole measurement setup as well as the integrated circuit under test, its environment (PCB, power supply) and the substrate model of each logic core. Simulation results and comparisons with measurement results demonstrate the validity of the suggested model. Moreover, they highlight the interest of the aforementioned protection strategies against electromagnetic disturbances.

Analysis of the propagation of electromagnetic disturbances inside integrated circuits using direct power injection and near-field scanning

This paper demonstrates how the direct power injection (DPI) and near-field scan (NFS) methods can be used to investigate the propagation of electromagnetic waves inside an integrated circuit (IC). In this study, a two-dimensional near-field cartography of the magnetic field generated by the circuit under test is achieved either in normal operation or while applying DPI into the Vdd pin of the IC, in order to visualize wave propagation. An unshielded (lidless) version of the test chip is used, making it easier to identify emission sources. Preliminary results demonstrate that the propagation of EM waves into a circuit depends not only on the impedance profile of the power supply network, but also on different EMI protection strategies implemented into the IC.

Automated extraction of the passive distribution network of an integrated circuit for the assessment of conducted electromagnetic emission

This paper introduces an automated extraction flow for the passive distribution network (PDN) of a complex integrated circuit. This extraction makes it possible to predict the propagation of external and internal electromagnetic disturbances on power supply networks inside the circuit and, consequently, to have a better knowledge of the conducted emission and immunity of this circuit. This method can be implemented in an industrial design flow. Comparisons between simulations and measurements demonstrate the validity of this approach.

Evaluation of countermeasures against electromagnetic analysis

The scope of this paper is twofold. (1) It aims at introducing a low cost near-field mapping system. This system scans automatically and dynamically, in both time and frequency domains, the magnetic field emitted by integrated circuits during the execution of any repetitive sequence of instructions. In the time domain, this system is used to automatically obtain a full chip Simple ElectroMagnetic Analysis (SEMA). (2) To describe the application of this system for the evaluation of certain design and technological countermeasures against malicious electromagnetic analyses.

Modeling of the substrate coupling path for direct power injection in integrated circuits

This paper presents a substrate coupling path model for the direct power injection (DPI) of EMI disturbances into the substrate of an integrated circuit (IC). This modeling is achieved on a 0.18 mum test chip composed of several functionally identical cores, differing only by their EMI protection strategies (RC protection, isolated substrate), and takes into account these different strategies. The comparison between simulation results and related measurements demonstrates that, once combined with the complete model of the injection set-up itself, these models are helpful to choose the best protection strategy against electromagnetic disturbances.