Fabrice Caignet

The challenge of signal integrity in deep-submicrometer CMOS technology

Advances in interconnect technologies, such as the increase in the number of metal layers, stacked vias, and the reduced routing pitch, have played a key role to continuously improve integrated circuit design and operating speed. However several parasitic effects jeopardize the benefits of scale-down. Understanding and predicting interconnect behavior is vital for designing high-performance integrated circuit design. Our paper first reviews the interconnect parasitic effects and examines their impact on circuit behavior and their increase due to lithography reduction, with special emphasis on propagation delay, lateral coupling, and crosstalk-induced delay. The problem of signal integrity characterization is then discussed. In our review of the different well-established measurement methodologies such as direct probing, S-parameters, e-beam sampling and on-chip sampling, we point out weaknesses, frequency ranges, drawbacks, and overall performances of these techniques. Subsequently, the on-chip sampling system is described. This features a precise line-domain characterization of the voltage waveform directly within the interconnect and shows its application in the accurate evaluation of propagation delay, crosstalk, and crosstalk-induced delay along interconnects in deep-submicrometer technology. The sensor parts are described in detail, together with signal integrity patterns and their implementation in 0.18-/spl mu/m CMOS technology. Measurements obtained with this technique are presented. In the third part, we discuss the simulation issues, describe the two- and three-dimensional interconnect modeling problems, and review the active device models applicable to deep-submicrometer technologies in order to agree on measurements and simulations. These studies result in a set of guidelines concerning the choice of interconnect models. The last part outlines the design rules to be used by designers and their implementation within computer-aided design (CAD) tools to achieve signal integrity compliance. From a 0.18-/spl mu/m technology are derived critical variables such as crosstalk tolerance margin, maximum coupling length, and the criteria for adding a signal repeater. From these, values for low-dielectric and copper interconnects have been selected.

On-chip sampling in CMOS integrated circuits

This paper presents a technique for precise crosstalk delay measurement based on on-chip sampling. Results obtained on a test chip fabricated in 0.7-/spl mu/m CMOS technology exhibit a 100% delay increase in a long coupled line configuration.

A new method for measuring signal integrity in CMOS ICs

The aim of this paper is to present a new and original method for on‐chip measurements of very high frequency parasitic signals where a sampling circuit is directly included in the test chip. The paper describes the usefulness of this sensor for measuring signal propagation and cross‐talk glitch on integrated circuit interconnects and also gives the results obtained experimentally.

On the measurement of crosstalk in integrated circuits

This paper describes a specific technique for measuring and characterizing the time-domain aspect of the crosstalk effect based on a sampling technique. It includes the description of the circuit implementation in 0.7 /spl mu/m technology and the measurements of the crosstalk between metallization tracks within the chip, with a 10 ps resolution and 10 mV precision. A comparison between the measurements and analog simulations based on a distributed RC model is also included. The key advantages of this technique are that it is totally integrated, fully static, and adaptable to any CMOS technology.

Characterization of crosstalk noise in submicron CMOS integrated circuits: an experimental view

A way to characterize the crosstalk noise susceptibility for integrated circuits fabrication technologies is presented. A comparison between 0.7- and 0.35-/spl mu/m technologies shows the increasing importance of crosstalk noise and, therefore, the need to consider this effect at the design level in submicron integrated circuits. An approach to measure the internal crosstalk generated by long metal interconnects based on using an RS latch sensor is proposed. An implementation and experimental measurements for 0.7-/spl mu/m technology are reported, confirming the very high noise peak values.

A System-Level Electrostatic-Discharge-Protection Modeling Methodology for Time-Domain Analysis

A system level modeling methodology is presented and validated on a simple case. It allows precise simulations of electrostatic discharge (ESD) stress propagation on a printed circuit board (PCB). The proposed model includes the integrated circuit (IC) ESD protection network, IC package, PCB lines, passives components, and externals elements. The impact of an external component on the ESD propagation paths into an IC is demonstrated. Resulting current and voltage waveforms are analyzed to highlight the interactions between all the elements of an operating PCB. A precise measurement technique was designed and used to compare with the simulation results. The model proposed in this paper is able to predict, with good accuracy, the propagation of currents and voltages into the whole system during ESD stress. It might be used to understand why failures occur and how to fix them with the most suitable solution.

ESD Standards: From Component to System

In this chapter, we look at the different ESD standards that are used for qualifying integrated circuits (ICs) and electronic systems. At the component level, these standards provide a guarantee that the IC is able to survive the various steps of assembly. This means that power is not supplied to the IC whilst it undergoes these different stresses. At the system level, the electronic board must be able to resist various ESD stresses both when the supply is on and when it is off. This results in two possible types of failure: physical or hard failure, which causes the destruction of the component, and functional or soft failure, which causes a temporary malfunction of the circuit.

4 – Modeling and Simulation Methods

: nThe efficiency of a protection strategy is largely dependent on the design approach implemented. For a long time, this approach was based on the experience of the designer and an empirical approach of trial and error could have a heavy impact on the price and the time to market of the product. The rise of computer-aided design tools and their simulation methods provides an approach that is more predictive of the ESD robustness of an integrated circuit and limits the number of design iterations associated with ESD protection.

3 – Protection Strategies Against ESD

: nIn the Introduction, we mentioned the various precautions that are taken in order to protect components and electronic systems from ESD. When the system is in its application environment, it no longer benefits from all these precautions, and protective structures must be put in place to protect it from potential ESD stresses.

CMOS chip for biomedical telemetry with hf power supply

This paper aims at describing a miniaturized CMOS implant- circuit for human medical telemetry. The chip includes a silicon antenna working on the principle of inductive coil coupling through the skin, an rf rectifier for power supply, an hf filter and logic circuitry for chip control. A CMOS compatible temperature sensor is included in the same chip. The obtained measurements are sent back to the coupled antenna and received outside the patients body. Two prototype chips have been designed in a CMOS 1.0 micrometer technology with encouraging results. The chips include the separate basic blocs of the micro-system: rectifier, integrated or external antenna, analog filters, sensors and logic systems.