Amir Nahir

A unified methodology for pre-silicon verification and post-silicon validation

The growing importance of post-silicon validation in ensuring functional correctness of high-end designs increases the need for synergy between the pre-silicon verification and post-silicon validation. We propose a unified functional verification methodology for the pre- and post-silicon domains. This methodology is based on a common verification plan and similar languages for test-templates and coverage models. Implementation of the methodology requires a user-directable stimuli generation tool for the post-silicon domain. We analyze the requirements for such a tool and the differences between it and its pre-silicon counterpart. Based on these requirements, we implemented a tool called Threadmill and used it in the verification of the IBM POWER7 processor chip with encouraging results.

Threadmill: a post-silicon exerciser for multi-threaded processors

Post-silicon validation poses unique challenges that bring-up tools must face, such as the lack of observability into the design, the typical instability of silicon bring-up platforms and the absence of supporting software (like an OS or debuggers). These challenges and the need to reach an optimal utilization of the expensive but very fast silicon platforms lead to unique design considerations - like the need to keep the tool simple and to perform most of its operation on platform without interaction with the environment. In this paper we describe a variety of novel techniques optimized for the unique characteristics of the silicon platform. These techniques are implemented in Threadmill - a bare-metal exerciser targeting multi-threaded processors. Threadmill was used in the verification of the POWER7 processor with encouraging results

Bridging pre-silicon verification and post-silicon validation

Post-silicon validation is a necessary step in a designs verification process. Pre-silicon techniques such as simulation and emulation are limited in scope and volume as compared to what can be achieved on the silicon itself. Some parts of the verification, such as full-system functional verification, cannot be practically covered with current pre-silicon technologies. This panel brings together experts from industry, academia, and EDA to review the differences and similarities between pre- and post-silicon, discuss how the fundamental aspects of verification are affected by these differences, and explore how the gaps between the two worlds can be bridged.

TAB-BackSpace: unlimited-length trace buffers with zero additional on-chip overhead

This paper presents TAB-BackSpace, our novel scheme to provide the effect of an unlimited-length trace buffer with no on-chip overhead beyond the existing debug logic. We present the theoretical foundation of our work, simulation studies on how we reduce the possibility of computing an erroneous trace, and results from the bring-up lab on real silicon of an IBM POWER7 processor, where TAB-BackSpace computes almost a thousand additional cycles of trace buffer information without any additional on-chip overhead.

Reaching coverage closure in post-silicon validation

Obtaining coverage information in post-silicon validation is a difficult task. Adding coverage monitors to the silicon is costly in terms of timing, power, and area, and thus even if feasible, is limited to a small number of coverage monitors. We propose a new method for reaching coverage closure in post-silicon validation. The method is based on executing the post-silicon exercisers on a pre-silicon acceleration platform, collecting coverage information from these runs, and harvesting important test templates based on their coverage. This method was used in the verification of IBMs POWER7 processor. It contributed to the overall high-quality verification of the processor, and specifically to the post-silicon validation and bring-up.

On cost-aware monitoring for self-adaptive load sharing

Monitoring is an essential part of any self-adaptive management loop. While providing the necessary information for making management decisions, monitoring itself incurs a cost in terms of the system and network resources committed to this management task. Thus, one can pose a generic question: what is the right amount of monitoring that maximizes its utility for management? This question turns out to be difficult to answer in general. In this paper we focus on quantifying the utility of monitoring for self-adaptive load sharing, where a stream of jobs arrives at a collection of n identical servers. We propose a novel model, that we dubbed an Extended Supermarket Model (ESM) to study the tradeoff between the usefulness of the monitoring information and the cost of obtaining it. We show that for each service request rate, there exists an optimal number of servers that should be monitored to obtain minimal average service time at an optimal cost. Using these findings, we present self-adaptive load-sharing algorithms both for centralized and fully distributed settings and evaluate these algorithms using simulations and a real testbed. Our results show that in realistic scenarios, where monitoring cost is not negligible, the self-adaptive load balancing is clearly superior to any cost-oblivious load-sharing mechanisms. We also demonstrate that in a fully distributed setting, where no dedicated monitoring component is employed, our self-adaptive heuristics perform very well with respect to the current common practice.

Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor

The growing importance of post-silicon validation in ensuring functional correctness of high-end designs has increased the need for synergy between the pre-silicon verification and post-silicon validation. This synergy starts with a common verification plan. It continues with common verification goals and shared tools and techniques. This paper describes our experience in improving this synergy in the pre- and post-silicon verification of IBMs POWER7 processor chip and by leveraging pre-silicon methodologies and techniques in the post-silicon validation of the chip.

Post-Silicon Validation of the IBM POWER8 Processor

The post-silicon validation phase in a processors design life cycle is geared towards finding all remaining bugs in the system. It is, in fact, our last opportunity to find functional and electrical bugs in the design before shipping it to customers. In this paper, we provide a high-level overview of the methodology and technologies put into use as part of the POWER8 post-silicon functional validation phase. We describe the results and list the primary factors that contributed to this highly successful bring-up.

Verification of Transactional Memory in POWER8

Transactional memory is a promising mechanism for synchronizing concurrent programs that eliminates locks at the expense of hardware complexity. Transactional memory is a hard feature to verify. First, transactions comprise several instructions that must be observed as a single global atomic operation. In addition, there are many reasons a transaction can fail. This results in a high level of non-determinism which must be tamed by the verification methodology. This paper describes the innovation that was applied to tools and methodology in pre-silicon simulation, acceleration and post-silicon in order to verify transactional memory in the IBM POWER8 processor core.

Optimizing test-generation to the execution platform

The role of stimuli generators is to reach all the dark corners of the design and expose the bugs hiding there. As such, stimuli generation is one of the cornerstones of dynamic verification. The quality of tools used for stimuli generation affect the outcome of the verification process. This paper discusses how differences between execution platforms, ranging from software simulators, through accelerators and emulators, to silicon affect the requirements of stimuli generators and how stimuli generators targeting different execution platforms address these differences. We demonstrate how the unique added value of the platforms are combined to guarantee the high quality of the silicon using examples of several IBM pre- and post-silicon stimuli generators with results from the verification of the IBM POWER7 processor chip.