Alon Vardi

InGaAs MOSFETs for CMOS: Recent advances in process technology

InGaAs has recently emerged as the most attractive non-Si n-channel material for future nano-scale CMOS. InGaAs n-channel MOSFETs promise to advance Moores Law by allowing continued scaling through a reduction in footprint and operating voltage without compromising performance. This paper reviews recent advances in some of the key enabling process technology of InGaAs MOSFETs. It also outlines some of the challenges that need to be overcome before this new device family can become a reality.

A Test Structure to Characterize Nano-Scale Ohmic Contacts in III-V MOSFETs

We propose and demonstrate a novel test structure to characterize the electrical properties of nano-scale metal-semiconductor contacts. The structure is in essence a two-port transmission line model (TLM) with contacts in the nanometer regime. Unlike the conventional TLM, two types of Kelvin measurements are possible. When performed on devices with different contact spacing, this allows the extraction of the contact resistance, the semiconductor sheet resistance, and the metal sheet resistance. For this, a 2-D distributed resistive network model has been developed. We demonstrate this technique in Mo/n+-InGaAs contacts with contact lengths from 19 to 450 nm where we have measured an average contact resistivity of 0.69±0.3 Ω·μm2. For relatively long contacts , this corresponds to an extremely small contact resistance of 6.6±1.6 Ω·μm.

Nanometer-Scale III-V MOSFETs

After 50 years of Moores Law, Si CMOS, the mainstream logic technology, is on a course of diminishing returns. The use of new semiconductor channel materials with improved transport properties over Si offer the potential for device scaling to nanometer dimensions and continued progress. Among new channel materials, III-V compound semiconductors are particularly promising. InGaAs is currently the most attractive candidate for future III-V based n-type MOSFETs while InGaSb is of great interest for p-channel MOSFETs. At the point of most likely deployment, devices based on these semiconductors will have a highly three-dimensional architecture. This paper reviews recent progress toward the development of nanoscale III-V MOSFETs based on InGaAs and InGaSb with emphasis on scalable technologies and device architectures and relevant physics. Progress in recent times has been brisk but much work remains to be done before III-V CMOS can become a reality.

InGaAs/InAs heterojunction vertical nanowire tunnel fets fabricated by a top-down approach

We demonstrate for the first time InGaAs/InAs heterojunction single nanowire (NW) vertical tunnel FETs fabricated by a top-down approach. Using a novel III-V dry etch process and gate-source isolation method, we have fabricated 50 nm diameter NW TFETs with a channel length of 60 nm and EOT=1.2 nm. Thanks to the insertion of an InAs notch, high source doping, high-aspect ratio nanowire geometry and scaled gate oxide, an average subthreshold swing (S) of 79 mV/dec at Vds= 0.3 V is obtained over 2 decades of current. On the same device, Ion= 0.27 μA/μm is extracted at Vdd= 0.3 V with a fixed Ioff= 100 pA/μm. This is the highest ON current demonstrated at this OFF current level in NW TFETs containing III-V materials.

A Diamond:H/MoO 3 MOSFET

A p-type MOSFET based on a heterointerface of hydrogenated-diamond transfer doped with MoO₃ (Diamond:H/MoO₃) is demonstrated for the first time. This is an important new heterostructure system due to its potentially improved temperature stability as compared with the better established Diamond:H/H₂O system. MOSFETs using HfO₂ as gate insulator show excellent output characteristics and gate control over the 2-D hole gas at the Diamond:H/MoO₃ interface. In 3.5-μm gate length devices, we obtain a maximum drain-current ON-OFF ratio of three orders of magnitude and a maximum transconductance of 2.5 μS/μm.

Sub-10-nm Fin-Width Self-Aligned InGaAs FinFETs

We study the scaling properties of self-aligned InGaAs FinFETs with sub-10-nm fin widths fabricated through a CMOS compatible front-end process. Working devices with fins as narrow as 7 nm, fin aspect ratios in excess of 5, and gate lengths as short as 20 nm have been fabricated using precision dry etching and digital etch. The devices feature self-aligned metal contacts that are 20-30 nm away from the edge of the gate. FinFETs with Lg = 30 nm, Wf = 7 nm, and channel height of 40 nm exhibit a transconductance of 900 μS/μm at VDS = 0.5 V. When normalized to Wf, this is a record value among all III-V FinFETs, indicating that our device architecture makes efficient use of conduction along the fin sidewalls.

Quantum-size effects in sub 10-nm fin width InGaAs FinFETs

InGaAs FinFETs with sub-10 nm fin widths were fabricated for the first time using precision dry etching and digital etch. We find that the threshold voltage, Vt, becomes highly sensitive to the fin width, Wf, in the sub-10 nm Wf range. 2D Poisson-Schrodinger simulations suggest that this is due to quantization effects. We also show that in the quantum regime, a sidewall slope below 850 significantly reduce Vt variation at the same drawn dimensions.

III-V MOSFETs for Future CMOS

In the last few years, as Si electronics faces mounting difficulties to maintain its historical scaling path, transistors based on III-V compound semiconductors have emerged as a credible alternative. To get to this point, fundamental technical problems had to be solved. Nevertheless, there are still many challenges that need to be addressed before the first non-Si CMOS technology becomes a reality. This paper reviews recent progress as well as challenges of III-V electronics for future logic applications.

High aspect ratio InGaAs FinFETs with sub-20 nm fin width

We demonstrate self-aligned InGaAs FinFETs with sub-20 nm fin width fabricated through a CMOS compatible front-end process. Working devices with fins as narrow as 7 nm, fin aspect ratios in excess of 5 and gate lengths as short as 20 nm have been fabricated using precision dry etching and digital etch. The devices also feature self-aligned metal contacts that are 20-30 nm away from the edge of the gate. FinFETs with Lg=30 nm, Wf=22 nm and channel height of 40 nm exhibit a transconductance of 1400 μS/μm at VDS=0.5 V. When normalized to Wf, this is a record value among all III-V FinFETs, indicating that our device architecture makes efficient use of conduction along the fin sidewalls.

Nanoscale Mo Ohmic Contacts to III–V Fins

A novel contact-first approach for III-V FinFETs and trigate MOSFETs is presented. In this process, the metal contact is sputtered on the as-grown semiconductor heterostructure, and the contact metal is used as a part of the fin dry-etch mask. We demonstrate this technique in Mo/n+-InGaAs contact structures with fin widths in the range of 50 to 300 nm. We have measured contact resistance in the range of 5 to 20Ω · μm. These results are in good agreement with the state-of-art contact resistance obtained on planar devices using similar technology. We further explore the possibility of enhancing the contacts by wrapping the metal over the fin sidewalls and found no significant improvement.