Andrew L. Sternberg

Charge Collection and Charge Sharing in a 130 nm CMOS Technology

Charge sharing between adjacent devices can lead to increased Single Event Upset (SEU) vulnerability. Key parameters affecting charge sharing are examined, and relative collected charge at the hit node and adjacent nodes are quantified. Results show that for a twin-well CMOS process, PMOS charge sharing can be effectively mitigated with the use of contacted guard-ring, whereas a combination of contacted guard-ring, nodal separation, and interdigitation is required to mitigate the NMOS charge sharing effect for the technology studied

HBD layout isolation techniques for multiple node charge collection mitigation

A three-dimensional (3D) technology computer-aided design (TCAD) model was used to simulate charge collection at multiple nodes. Guard contacts are shown to mitigate the charge collection and to more quickly restore the well potential, especially in PMOS devices. Mitigation of the shared charge collection in NMOS devices is accomplished through isolation of the P-wells using a triple-well option. These techniques have been partially validated through heavy-ion testing of three versions of flip-flop shift register chains.

A Bias-Dependent Single-Event Compact Model Implemented Into BSIM4 and a 90 nm CMOS Process Design Kit

A single-event model capable of capturing bias- dependent effects has been developed and integrated into the BSIM4 transistor model and a 90 nm CMOS process design kit. Simulation comparisons with mixed mode TCAD are presented.

Single Event Upsets in Deep-Submicrometer Technologies Due to Charge Sharing

Circuit and 3D technology computer aided design mixed-mode simulations show that the single event upset vulnerability of 130- and 90-nm hardened latches to low linear energy transfer (LET) particles is due to charge sharing between multiple nodes as a result of a single ion strike. The low LET vulnerability of the hardened latches is verified experimentally.

Directional Sensitivity of Single Event Upsets in 90 nm CMOS Due to Charge Sharing

Heavy-ion testing of a radiation-hardened-by-design (RHBD) 90 nm dual interlocked cell (DICE latch) shows significant directional sensitivity results impacting observed cross-section and LET thresholds. 3-D TCAD simulations show this directional effect is due to charge sharing and parasitic bipolar effects due to n-well potential collapse.

Comparison of SETs in bipolar linear circuits generated with an ion microbeam, laser light, and circuit simulation

Generally good agreement is obtained between the single-event output voltage transient waveforms obtained by exposing individual circuit elements of a bipolar comparator and operational amplifier to an ion microbeam, a pulsed laser beam, and circuit simulations using SPICE. The agreement is achieved by adjusting the amounts of charge deposited by the laser or injected in the SPICE simulations. The implications for radiation hardness assurance are discussed.

Heavy Ion Testing and Single Event Upset Rate Prediction Considerations for a DICE Flip-Flop

Monte-Carlo simulation using the MRED software suite, coupled with SPICE analysis, is used to identify internal mechanisms of SEU in DICE flip-flops. Low frequency cross-section measurements and simulations identify multiple-node charge collection SEU mechanisms as the dominant contributor. An increasingly isotropic response is predicted with increasing frequency due to latching of internal single-node transients near clock boundaries. Implications for heavy ion testing and SEU rate prediction are presented.

Critical charge for single-event transients (SETs) in bipolar linear circuits

The critical charge for single-event transients (SETS) from heavy ions has been simulated and measured in bipolar linear circuits under several bias conditions. Although in many cases the threshold linear energy transfer is less than 2 MeV-cm/sup 2//mg, the minimum critical charge is of the order of 0.3-1 pC.

Integrating Circuit Level Simulation and Monte-Carlo Radiation Transport Code for Single Event Upset Analysis in SEU Hardened Circuitry

Monte-Carlo radiation transport code is coupled with SPICE circuit level simulation to identify regions of single event upset vulnerability in an SEU hardened flip-flop, as well as predict single event upset cross sections and on-orbit soft error rates under static and dynamic operating conditions.

The role of parasitic elements in the single-event transient response of linear circuits

Parasitic elements can play an important role in the single-event transient sensitivity of a circuit. This work describes how parasitics can affect the simulation response of linear circuits and shows how parasitics have been identified using a pulsed laser.