Wenjie Lu

InGaAs MOSFETs for CMOS: Recent advances in process technology

InGaAs has recently emerged as the most attractive non-Si n-channel material for future nano-scale CMOS. InGaAs n-channel MOSFETs promise to advance Moores Law by allowing continued scaling through a reduction in footprint and operating voltage without compromising performance. This paper reviews recent advances in some of the key enabling process technology of InGaAs MOSFETs. It also outlines some of the challenges that need to be overcome before this new device family can become a reality.

A Test Structure to Characterize Nano-Scale Ohmic Contacts in III-V MOSFETs

We propose and demonstrate a novel test structure to characterize the electrical properties of nano-scale metal-semiconductor contacts. The structure is in essence a two-port transmission line model (TLM) with contacts in the nanometer regime. Unlike the conventional TLM, two types of Kelvin measurements are possible. When performed on devices with different contact spacing, this allows the extraction of the contact resistance, the semiconductor sheet resistance, and the metal sheet resistance. For this, a 2-D distributed resistive network model has been developed. We demonstrate this technique in Mo/n+-InGaAs contacts with contact lengths from 19 to 450 nm where we have measured an average contact resistivity of 0.69±0.3 Ω·μm2. For relatively long contacts , this corresponds to an extremely small contact resistance of 6.6±1.6 Ω·μm.

Nanometer-Scale III-V MOSFETs

After 50 years of Moores Law, Si CMOS, the mainstream logic technology, is on a course of diminishing returns. The use of new semiconductor channel materials with improved transport properties over Si offer the potential for device scaling to nanometer dimensions and continued progress. Among new channel materials, III-V compound semiconductors are particularly promising. InGaAs is currently the most attractive candidate for future III-V based n-type MOSFETs while InGaSb is of great interest for p-channel MOSFETs. At the point of most likely deployment, devices based on these semiconductors will have a highly three-dimensional architecture. This paper reviews recent progress toward the development of nanoscale III-V MOSFETs based on InGaAs and InGaSb with emphasis on scalable technologies and device architectures and relevant physics. Progress in recent times has been brisk but much work remains to be done before III-V CMOS can become a reality.

III-V MOSFETs for Future CMOS

In the last few years, as Si electronics faces mounting difficulties to maintain its historical scaling path, transistors based on III-V compound semiconductors have emerged as a credible alternative. To get to this point, fundamental technical problems had to be solved. Nevertheless, there are still many challenges that need to be addressed before the first non-Si CMOS technology becomes a reality. This paper reviews recent progress as well as challenges of III-V electronics for future logic applications.

High aspect ratio InGaAs FinFETs with sub-20 nm fin width

We demonstrate self-aligned InGaAs FinFETs with sub-20 nm fin width fabricated through a CMOS compatible front-end process. Working devices with fins as narrow as 7 nm, fin aspect ratios in excess of 5 and gate lengths as short as 20 nm have been fabricated using precision dry etching and digital etch. The devices also feature self-aligned metal contacts that are 20-30 nm away from the edge of the gate. FinFETs with Lg=30 nm, Wf=22 nm and channel height of 40 nm exhibit a transconductance of 1400 μS/μm at VDS=0.5 V. When normalized to Wf, this is a record value among all III-V FinFETs, indicating that our device architecture makes efficient use of conduction along the fin sidewalls.

Nanoscale Mo Ohmic Contacts to III–V Fins

A novel contact-first approach for III-V FinFETs and trigate MOSFETs is presented. In this process, the metal contact is sputtered on the as-grown semiconductor heterostructure, and the contact metal is used as a part of the fin dry-etch mask. We demonstrate this technique in Mo/n+-InGaAs contact structures with fin widths in the range of 50 to 300 nm. We have measured contact resistance in the range of 5 to 20Ω · μm. These results are in good agreement with the state-of-art contact resistance obtained on planar devices using similar technology. We further explore the possibility of enhancing the contacts by wrapping the metal over the fin sidewalls and found no significant improvement.

Ultralow Resistance Ohmic Contacts for p-Channel InGaSb Field-Effect Transistors

We demonstrate ultralow ohmic contact resistance to antimonide-based, p-channel quantum-well field-effect transistor (QW-FET) structures using a new p^±-InAs/InAsSb cap structure. The incorporation of a p^±-InAsSb layer enables the use of a thicker cap with lower sheet resistance, resulting in an improved contact resistivity. Using a Pd-based ohmic scheme, the composite cap structure resulted in a 4x reduction in contact resistance compared with a standard p^±-InAs cap. This translates into nearly 3x improvement in the gm of fabricated InGaSb p-channel QW-FETs. Furthermore, Ni contacts on the composite cap were fabricated and a contact resistance of 45 Ω · μm was obtained. An accurate contact resistivity extraction in this very low range is possible through nanotransmission line models with sub-100 nm contacts. In devices of this kind with Ni-based contacts, we derive an ultralow contact resistivity of 5.2 · 10^-8 Ω · cm².

Alcohol-Based Digital Etch for III–V Vertical Nanowires With Sub-10 nm Diameter

This letter introduces a novel alcohol-based digital etch technique for III–V FinFET and nanowire MOSFET fabrication. The new technique addresses the limitations of the conventional water-based approach in enabling structures with sub-10-nm 3-D features. Using the same oxidation step, the new technique shows an etch rate of 1 nm/cycle, identical to the conventional approach. Sub-10 nm fins and nanowires with a high mechanical yield have been achieved. InGaAs nanowires with a diameter of 5 nm and an aspect ratio greater than 40 have been demonstrated. The new technique has also been successfully applied to InGaSb-based heterostructures, the first demonstration of digital etch in this material system. Vertical InGaAs nanowire gate-all-around MOSFETs with a subthreshold swing of 70 mV/decade at

High hole mobility in strained In0.25Ga0.75Sb quantum well with high quality Al0.95Ga0.05Sb buffer layer

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CMOS beyond Si: Nanometer-Scale III-V MOSFETs

50 mV have been obtained at a nanowire diameter of 40 nm, demonstrating the good interfacial quality that the new technique provides.