Jesus A. del Alamo

Nanometer-Scale III-V MOSFETs

After 50 years of Moores Law, Si CMOS, the mainstream logic technology, is on a course of diminishing returns. The use of new semiconductor channel materials with improved transport properties over Si offer the potential for device scaling to nanometer dimensions and continued progress. Among new channel materials, III-V compound semiconductors are particularly promising. InGaAs is currently the most attractive candidate for future III-V based n-type MOSFETs while InGaSb is of great interest for p-channel MOSFETs. At the point of most likely deployment, devices based on these semiconductors will have a highly three-dimensional architecture. This paper reviews recent progress toward the development of nanoscale III-V MOSFETs based on InGaAs and InGaSb with emphasis on scalable technologies and device architectures and relevant physics. Progress in recent times has been brisk but much work remains to be done before III-V CMOS can become a reality.

Negative-bias temperature instability of GaN MOSFETs

We present a detailed study of the threshold voltage (Vt) instability of GaN n-MOSFETs under negative gate stress. We have investigated Vt shift, subthreshold swing (S) degradation and transconductance (gm) degradation under negative gate voltage stress of different duration at different stress voltages and temperatures. We have found that as stress duration, voltage magnitude and temperature increase, Vt shift (ΔVT) progresses through three regimes. Under low-stress, ΔVT is negative and recoverable, which is a result of electron detrapping from pre-existing oxide traps. Under mid-stress, ΔVT is positive and also recoverable. This appears to be due to temporary electron trapping in the GaN channel under the edges of the gate. For high-stress, there is an additional non-recoverable negative ΔVT, which is consistent with interface state generation.

Analysis of Resistance and Mobility in InGaAs Quantum-Well MOSFETs From Ballistic to Diffusive Regimes

Recent advances in the fabrication technology have yielded nanometer-scale InGaAs quantum-well (QW) MOSFETs with extremely low and reproducible external contact and access region resistances. This allows, for the first time, a detailed analysis of the role of ballistic transport in the operation of these devices. This paper presents a systematic analysis of external resistance, ballistic resistance, and channel mobility in InGaAs QW-MOSFETs under near-equilibrium conditions, i.e., under very low drain-source bias. This is an important regime for device characterization. Devices with a wide range of channel lengths, from 70 to 650 nm, are investigated. Our analysis includes the consideration of the impact of carrier degeneracy in the QW channel. We show that unless the ballistic behavior in the intrinsic channel is accounted for, the standard extraction technique for external resistance grossly exaggerates its value as it incorporates the so-called ballistic resistance. By separating out the ballistic resistance, the external resistance in our devices is shown to be extremely low, 74 Ω-μm, including both source and drain sides. This is thanks to our contact-first self-aligned Mo-contact technology. Furthermore, taking the advantage of the wide range of ballisticity of the devices studied in this paper, we demonstrate a methodology to self-consistently extract scattering-dependent effective mobility, mean-free-path length, and ballistic mobility.

Sub-10-nm Fin-Width Self-Aligned InGaAs FinFETs

We study the scaling properties of self-aligned InGaAs FinFETs with sub-10-nm fin widths fabricated through a CMOS compatible front-end process. Working devices with fins as narrow as 7 nm, fin aspect ratios in excess of 5, and gate lengths as short as 20 nm have been fabricated using precision dry etching and digital etch. The devices feature self-aligned metal contacts that are 20-30 nm away from the edge of the gate. FinFETs with Lg = 30 nm, Wf = 7 nm, and channel height of 40 nm exhibit a transconductance of 900 μS/μm at VDS = 0.5 V. When normalized to Wf, this is a record value among all III-V FinFETs, indicating that our device architecture makes efficient use of conduction along the fin sidewalls.

Progressive breakdown in high-voltage GaN MIS-HEMTs

We have investigated the time-dependent dielectric breakdown (TDDB) characteristics of high-voltage AlGaN/GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors (MIS-HEMTs). We focus in particular on the phenomenon known as progressive breakdown (PBD), marked by an onset of noise in the gate current IG during forward gate bias stress. We observe classic PBD behavior characterized by a rapid increase of IG noise during stress that takes place soon before hard breakdown (HBD). The onset of PBD also marks a change in the subthreshold characteristics of the transistor: the gate leakage increases above the measurement noise floor in a step-like fashion, with this additional leakage flowing out the source and/or drain terminals. After PBD, the subthreshold IG also shows a power law temperature dependence. The capacitance-voltage characteristics measured both before and after PBD confirm that device degradation does not occur at the AlGaN/GaN interface. All results are consistent with observations in silicon MOSFETs that support the percolation model of defects behind PBD and HBD. This gives hope that proper physical models suitable for lifetime estimation can be developed for TDDB in GaN MIS-HEMTs.

Electrical Degradation of InAlN/GaN HEMTs Operating Under ON Conditions

The degradation of InAlN/GaN high-electron-mobility transistors (HEMTs) for millimeter-wave applications has been examined under on conditions. Two dominant permanent degradation mechanisms have been identified as well as two trapping mechanisms which affect the device characteristics in different ways. Under high-voltage, low-current stress conditions, we have observed permanent enhancement in the maximum drain current IDmax that arises from a negative shift in threshold voltage VT. We attribute this mechanism to depassivation of hydrogenated defects. Under the same stress conditions, there is prominent and reversible hot-electron trapping on the drain side of the device that brings IDmax down and increases the drain resistance. Under low-voltage high-current stress conditions, there is a visible permanent reduction in IDmax and a positive shift in VT. This is also the signature of-high temperature stress under unbiased conditions and is attributed to gate sinking.

An InGaSb p-channel FinFET

We demonstrate the first InGaSb p-channel FinFET. Towards this goal, we have developed a fin dry-etch technology which yields fins as narrow as 15 nm with vertical sidewalls, an aspect ratio greater than 10 and low sidewall interface state density. We have also realized Si-compatible ohmic contacts with ultra-low contact resistivity of 3.5-10-8 Q-cm2. InGaSb FinFETs with fin widths down to 30 nm and gate lengths down to 100 nm have been fabricated. The Al2O3 gate oxide has an EOT of 1.8 nm. A high gm of 122 μS/μm is obtained in devices of Wf = 100 nm and Lg = 100 nm. In the smallest devices with Wf = 30 nm and Lg = 100 nm, a gm of 78 μS/μm is achieved.

High aspect ratio InGaAs FinFETs with sub-20 nm fin width

We demonstrate self-aligned InGaAs FinFETs with sub-20 nm fin width fabricated through a CMOS compatible front-end process. Working devices with fins as narrow as 7 nm, fin aspect ratios in excess of 5 and gate lengths as short as 20 nm have been fabricated using precision dry etching and digital etch. The devices also feature self-aligned metal contacts that are 20-30 nm away from the edge of the gate. FinFETs with Lg=30 nm, Wf=22 nm and channel height of 40 nm exhibit a transconductance of 1400 μS/μm at VDS=0.5 V. When normalized to Wf, this is a record value among all III-V FinFETs, indicating that our device architecture makes efficient use of conduction along the fin sidewalls.

Ultrathin Body InGaAs MOSFETs on III-V-On-Insulator Integrated With Silicon Active Substrate (III-V-OIAS)

Thin-body self-aligned InGaAs MOSFETs are fabricated on a III-V-On-Insulator structure on a silicon active substrate (III-V-OIAS). The p-type Si active substrate acts as a back gate that can modulate the threshold voltage and other electrical characteristics of the device. This paper explores the physics behind this effect through 2-D simulations and comparison with experiments. In the off-state, we find that the application of a positive body-to-source (Vbs) voltage increases the subthreshold swing but reduces drain-induced barrier lowering. The first effect is related to the electron profile and the location of the centroid of electron charge in the channel while the second is closely associated with the modulation of a depletion region in the silicon substrate. In the on-state, the series resistance is observed to improve under positive Vbs due to the increased accumulation of electrons in the extrinsic portion of the device. In addition, the channel mobility exhibits a two-branch behavior in its dependence on the average vertical electric field in the channel. This is explained by the different interfacial scattering that takes place at the front and back channel surfaces. This paper highlights the tradeoffs involved in attempting to exploit the body bias in the operation of QW-MOSFETs in III-V-On-Insulator with active substrate.

OFF-state TDDB in high-voltage GaN MIS-HEMTs

We have investigated time-dependent dielectric breakdown (TDDB) in high-voltage AlGaN/GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors (MIS-HEMTs) biased in the OFF state. This is an important reliability concern that has been overlooked. Towards this goal, we have developed a novel methodology using ultraviolet light that allows us to separate the permanent effects of dielectric degradation from the transient behavior due to trapping after high voltage stress. This new approach reveals unmistakable evidence of TDDB at the drain end of the gate in the OFF state. This mechanism must be accounted for in device lifetime estimation models. Furthermore, trapping emerges as a significant complication in the study of OFF-state TDDB. If uncontrolled, trapping effects can lead to a dramatic overestimation of device breakdown voltage.