Altaf Hasan

High performance package designs for a 1 GHz microprocessor

This paper describes the architecture and design of an organic land grid array (OLGA) and a flip chip pin grid array (FCPGA) package for a 32 b microprocessor with a clock frequency of 1 GHz and an I/O bus designed to run at 133 MHz. Cost and performance targets and compatibility with existing systems are the key accomplishments of this design project. Issues and implementation details of each of these aspects are discussed and contrasted here. This paper concentrates on the processor performance issues associated with the package routing and power delivery. To overcome high inductance associated with the socket and package pins in the FCPGA package, decoupling capacitors were placed on the underside of the package substrate. This paper discusses an optimal placement scheme for the capacitors and their effectiveness in performance improvement of the system compared to the OLGA package case.

Dual die Pentium D package technology development

This paper describes the technology development for packaging two identical CPU die on one package. Historically, processors involved packaging one die on a package, but with higher performance demands, multiple die products have become necessary. With existing single core die designs, packaging two die in one unit provides a novel way of producing a dual core CPU without designing new silicon. This paper starts with the evolution of dual core CPU from use of two die joined to each other to separate die placed next to each other to the final form of two die placed with a gap. The land grid array (LGA) package technology development was done within the boundary conditions of reuse of existing sockets and enabling solutions. It involved use of higher layer count substrates to allow routing of two die to pre-existing pin-out, modified IHS to accommodate two die in a limited space, and die side components for helping power delivery. The paper describes the details of the substrate technology, routing options and design rules to meet the dual die package requirements that include product performance, substrate manufacturing and assembly and test. The test vehicle definition and design of different structures are described that are new for the dual die scenario. Also limitations based upon compatibility requirements for test lead to creative implementations of those test vehicle structures. The IHS design modifications implemented to fit the two die and to maintain the over all package stack-up are described. Routing and power delivery methodologies in the dual die package architecture are described. Discussed also are how substrate design rules, & collaterals and design process changed and adjusted to the move from a single die to two. The paper then focuses on the multiple challenges faced by the assembly and reliability areas. Single chip package versus dual chip package mechanical stresses are compared. Assembly areas of chip attach, under-fill, and IHS attach are described. The process design rules for UF in dual die case are new compared with the single die case. The challenges of IHS attach and TIM process (including thicknesses) for the two separate die are addressed. Specific challenges encountered for multi-chip packages (MCP) include application of chip attach flux, removal of flux after chip attach as well as voids formed at the TIM to IHS interface. Finally, thermal performances of the dual die package are presented and compared with that of a single die package. The thermal definitions and measurement methods for the dual die package are shown with equivalents to single die case. The thermal benefits of a dual die package prove the advantages of a dual die package in terms of product performance with respect to power dissipation. The future directions of the dual die technology based on the new products on the roadmap are discussed along with some potential areas of focus in the next generation dual die packages

Pentium 4 processor package design and development

Intel Pentium 4 ushered a new IA-32 architecture with a jump in performance from the previous generation microprocessors. Higher core frequency, higher bus speed and new architecture features needed very competitive package designs. The demand on packaging tu match such product performance necessitated development of new technologies. This paper describes development and implementation of package technologies for two generations of silicon processes of Pentium 4 as well as for intra-process shrink variations of the die for various applications. Pentium 4 is the new IA-32 architecture processor for use in multiple platforms. In addition to Desktop and Mobile segments, enhanced versions are for use in workstation and server systems also. The Mobile market segment is further divided into Full Feature, Thin & Light and Mini-Note sub-segments with the respective Performance and Value subdivisions. Likewise, the Desktop segment is divided into Performance, Mainstream and Value subsegments whereas the IA-32 Server segment is subdivided into UP (Uni-Processor), DP (Dual-Processor) & MP (Multi-Processor) catering different market sub-segments. Pentium 4 debuted in 0.18 p Si process with successive migration to 0.13 p process. It had a roadmap of progressively higher clock frequencies and bus frequencies. The initial packaging for 0.18 pm process Pentium 4 was done using an Interposer type package. which consisted of an OLGA substrate with (flipchipattached die) surface mounted on a (through-pin type) PGA interposer at 1.27 mm diagonal pitch. This twc-part solution looked unattractive from overall package parasitics as well as line item management perspectives. Therefore, a new organic PGA package called FCPGA was employed with surface mount attached pins at 1.27 mm square pitch. This enabled achieving a socketahle package with a single piece part. In addition to eliminating 2 piece parts for packaging, this new package allowed the body size reduction from 53.3 mm to 35.0 mm. It also dramatically improved the package and pin parasitics to allow more robust electrical performance. The product architecture employs the Nethurst architecture for turbo performance. The overall power associated with the processor, along with the dddt posed a challenge for the package design. The methodology of designing decoupliig capacitor schemes for the packages is described. Power delivery improvement was a major part of the design analysis activities with the package and system level issues considered. VO performance was analyzed for different design feature parameters ensuring signal integrity. Optimization of design rules for balancing the layout and cost drivers is described. b The product performance and cost in the 0.18 pn Si process were optimized by successive die shrinks. The packaging approach to address such cases is also discussed. The socket parameters for the two package types are also compared. The package model and simulation results for package parameter variation are shown. The thermal-electrical reliability aspects of the package parameters were considered to ensure that the package would perform reliably both on a global and local basis. This was especially important in view of the significant power density variation and current demand variation over the die area. Thermal power management was challenging due to the system level cost constraints. Thermal interface material development done for improved thermal resistances is described with the thermal solutions of the packages described briefly. Finally, the future direction of packaging for Intel processors is discussed.

BGA package ball field interaction with manufacturing and design

The ball field design in a flip chip (FC) ball grid array (BGA) often becomes the determining factor for the package body size. This paper describes the physical definition of ball fields for different integrated circuit (IC) product types, and the implications of the same on the package reliability. The printed circuit board (PCB) technology in terms of the manufacturing processes, design rules, and cost is a major factor in the determination of the BGA ball field design. It is the PCB level routing impact that can ultimately dictate the pitches and distribution to be used for the FCBGA ball fields and hence the array size. Optimization of package size and board routing can be achieved using different techniques, and these are discussed in detail. Lastly, in choosing the package size and ball field, the BGA coplanarity concerns, induced by the dynamic package warpage, causing solder joint failures during board assembly, and stress, as well as some manufacturing and test driven ball pattern design rules, impacting solder joint reliability (SJR), are discussed.

High performance Mobile Pentium/spl reg/ III package development and design

Package development and design issues for Mobile Pentium/spl reg/ III processors are described in this paper focusing on the processor using 0.13 /spl mu/m silicon process technology. The development of the flip chip (FC) pin grid array (PGA) version as well as the ball grid array (BGA) version of the packages used for different sub-segments of the mobile market are discussed. First, the form factors of the packages are described highlighting some of the new features of each package. The new body size of 35 mm and pin field set forth a new form factor at Intel and a 1.27 mm square pitch PGA package used for these mobile products is an industry first. The package layout, the signal routing methods, the power delivery scheme, the decoupling capacitor placements and the impact of package geometry on the package performance are described. The signal integrity and the power supply considerations for high frequency applications are discussed. The die side placement of decoupling capacitors in BGA and the pin side placement of decoupling capacitors in PGA packages are described. A multi-terminal capacitor with improved inductance is introduced in the packages. Performance issues are analyzed and compared for the selected capacitor type for each package.

IXP2400 network processor package development

This paper describes the application and performance of network processors (NPU) and the development of packaging for the new IXP2400 NPUs. Flip chip interconnect packaging, applied first time to Intel NPUs, is described. The package used for very high I/O and ball count with a 1.0 mm pitch fully populated BGA is a first in its class. The details of the package substrate design are described and the package substrate characteristics along with validation are discussed. High ambient temperature for certain applications was specially challenging for cooling solutions. The techniques applied to circumvent packaging problems are described in the paper which include alignment of the package with the market demand and reconciling the silicon reliability for such solutions. The issues related to solder joint reliability for a 1.0 mm pitch BGA and its interactions with board level enabling are discussed with methods considered to improve it. Finally, the future direction of NPU products and the demands on packaging are listed.

IXE 7000 Ethernet switch package development

The IXE74242 is a device in the IXE 7000 product line targeted for high performance Layer 2/3/4 Ethernet communication switching with 24 /spl times/ 1G b/s and 2 /spl times/ 10 Gb/s ports. It is Intel Communication Group ESO divisions first 90 nm switch built in a 42.5 mm flip chip package. This paper describes the IXE74242 product and package development challenges in developing successful first working silicon on Intels 90 nm mixed signal silicon platform.