Ajit V. Sathe

High performance Mobile Pentium/spl reg/ III package development and design

Package development and design issues for Mobile Pentium/spl reg/ III processors are described in this paper focusing on the processor using 0.13 /spl mu/m silicon process technology. The development of the flip chip (FC) pin grid array (PGA) version as well as the ball grid array (BGA) version of the packages used for different sub-segments of the mobile market are discussed. First, the form factors of the packages are described highlighting some of the new features of each package. The new body size of 35 mm and pin field set forth a new form factor at Intel and a 1.27 mm square pitch PGA package used for these mobile products is an industry first. The package layout, the signal routing methods, the power delivery scheme, the decoupling capacitor placements and the impact of package geometry on the package performance are described. The signal integrity and the power supply considerations for high frequency applications are discussed. The die side placement of decoupling capacitors in BGA and the pin side placement of decoupling capacitors in PGA packages are described. A multi-terminal capacitor with improved inductance is introduced in the packages. Performance issues are analyzed and compared for the selected capacitor type for each package.