Ananda Sarangi

High performance package designs for a 1 GHz microprocessor

This paper describes the architecture and design of an organic land grid array (OLGA) and a flip chip pin grid array (FCPGA) package for a 32 b microprocessor with a clock frequency of 1 GHz and an I/O bus designed to run at 133 MHz. Cost and performance targets and compatibility with existing systems are the key accomplishments of this design project. Issues and implementation details of each of these aspects are discussed and contrasted here. This paper concentrates on the processor performance issues associated with the package routing and power delivery. To overcome high inductance associated with the socket and package pins in the FCPGA package, decoupling capacitors were placed on the underside of the package substrate. This paper discusses an optimal placement scheme for the capacitors and their effectiveness in performance improvement of the system compared to the OLGA package case.

High performance Mobile Pentium/spl reg/ III package development and design

Package development and design issues for Mobile Pentium/spl reg/ III processors are described in this paper focusing on the processor using 0.13 /spl mu/m silicon process technology. The development of the flip chip (FC) pin grid array (PGA) version as well as the ball grid array (BGA) version of the packages used for different sub-segments of the mobile market are discussed. First, the form factors of the packages are described highlighting some of the new features of each package. The new body size of 35 mm and pin field set forth a new form factor at Intel and a 1.27 mm square pitch PGA package used for these mobile products is an industry first. The package layout, the signal routing methods, the power delivery scheme, the decoupling capacitor placements and the impact of package geometry on the package performance are described. The signal integrity and the power supply considerations for high frequency applications are discussed. The die side placement of decoupling capacitors in BGA and the pin side placement of decoupling capacitors in PGA packages are described. A multi-terminal capacitor with improved inductance is introduced in the packages. Performance issues are analyzed and compared for the selected capacitor type for each package.

Design and performance evaluation of Pentium/sup R/ III microprocessor packaging

This paper describes a design methodology to determine the number of chip capacitors needed and its placement scheme for the latest Pentium/sup R/ III microprocessor package substrate for optimum performance. The effect of capacitors on the power supply and its performance and placement schemes are discussed and compared against measurements. Performance improvements are outlined and compared between the current 0.13 /spl mu/m and the previous 0.18 /spl mu/m silicon package technology designed for compatibility with existing systems.

Power level management in an IA32 microprocessor

The power delivery system of a recent IA32 microprocessor is described. The microprocessor takes advantage of voltage positioning and selects its own operating voltage dynamically to optimize performance while maintaining reliability. This capability is used by the processor to change its operating voltage and frequency during normal operation.

Design and Performance Analysis of Dual Die Pentium® 4 Package

The continued growth of power consumption has presented numerous packaging challenges for high performance processors. Even though voltage is a strong knob to reduce power, reducing voltage also reduces the maximum operating frequency (M. Suryakumar et al., 2006). Integrating more cores into the processor would result in better performance and power efficiency but this requires more memory accesses, driving a need for larger cache and high speed signaling, increasing package size and layer count. This paper discusses the design strategy for power delivery and compares performance of the dual die packages through measurements

Chip-package codesign with redistribution layer

The use of redistribution layers to connect I/O circuit to the I/O pad is introduced and the electrical performance of a conceptual design with and without signal redistribution was compared.

The Impact of Leakage to the Power Supply Impedance of a Microprocessor

This paper shows that the resonant behavior of a microprocessors power supply is strongly influenced by both the leakage and the dynamic power of the microprocessor. As a result of this, the peak package power supply impedance is a function of the operating conditions of the microprocessor. Measurements on a 65 nm Intelreg Pentiumreg 4 microprocessor have been used to quantify this behavior

Maintaining microprocessor compatibility across process generations

This paper presents two approaches that have been used to maintain socket compatibility between a pair of microprocessors operating at different supply voltages. A current balancing scheme to keep independent regulators within their specified operating range when shorted through the microprocessor socket is presented. Using a network of termination resistors in the microprocessors package, an operating scheme was developed such that minimum regulation current requirements could be met and a balanced current environment could be achieved inside two different switching regulators operating at different frequencies. The design and the implementation details of the current balancing method in the microprocessor is described and compared with measured data.