Gregory F. Taylor

A 1.05 V 1.6 mW, 0.45

Monitoring temperature in a microprocessor is important for optimal energy consumption under various workloads. This paper presents a temperature sensor in a 32 nm high-k metal gate digital CMOS process for integration in a microprocessor core. The sensor uses a ratio of currents driven into a BJT pair with current chopping to up-convert the temperature signal. A second order sigma-delta (ΣΔ) 1-bit ADC is used to digitize the chopped signal, which is then down-converted and filtered in the digital domain to obtain a temperature measurement. The sensor operates from -10 to 110°C, achieving a 3σ resolution of 0.45°C, and ≪5°C inaccuracy without calibration/trimming.

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A review of high fan-in circuit design in contemporary logic technologies is presented. This is followed by a description of BiNMOS circuit structures which allow the construction of large fan-in, logical AND or OR functions. The first is a dynamic design, while the second is static. Application of the former in a 3.3 V, 100 MHz, implementation of the Pentium Microprocessor on a 0.6 /spl mu/m BiNMOS process is described, while application of the latter in a 0.35 /spl mu/m BiNMOS implementation is presented. Power and reliability considerations such as bipolar junction transistors (BJT), reverse V/sub bc/, and MOS hot electron protection are included.

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This paper describes the architecture and design of an organic land grid array (OLGA) and a flip chip pin grid array (FCPGA) package for a 32 b microprocessor with a clock frequency of 1 GHz and an I/O bus designed to run at 133 MHz. Cost and performance targets and compatibility with existing systems are the key accomplishments of this design project. Issues and implementation details of each of these aspects are discussed and contrasted here. This paper concentrates on the processor performance issues associated with the package routing and power delivery. To overcome high inductance associated with the socket and package pins in the FCPGA package, decoupling capacitors were placed on the underside of the package substrate. This paper discusses an optimal placement scheme for the capacitors and their effectiveness in performance improvement of the system compared to the OLGA package case.

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The performance of CMOS integrated circuits has always been, and continues to be, limited by reliability considerations. Performance, reliability, and cost are traded off through voltage and temperature specifications. Higher operating voltage raises performance but impacts reliability both directly and through increased temperatures unless extra cooling is supplied. Lower temperatures yield higher performance and higher reliability but also higher cost. As silicon technology scales, these trade-offs are becoming more pronounced. While hot carrier injection may be becoming less significant as semiconductor technology scales to thinner gate oxides, other mechanisms are becoming more significant. The temperature acceleration of oxide breakdown is increasing with decreasing thickness (Degraeve et al., 1999), current densities are increasing, further stressing electromigration, and inductive noise effects are becoming more significant, while soft error susceptibility is increasing (Dai et al., 1999). There are many mechanisms that can lead to the failure of an integrated circuit. Hot carrier injection has been a significant issue, but has been surpassed by other mechanisms as CMOS technology has advanced into the deep submicron regime. In this paper, we focus mainly on the design and validations issues associated with oxide wear-out failure mechanisms.

Resolution

In this paper, we present the design approach and an empirical validation of the power supply decoupling network with particular emphasis on on-die capacitance. The impact of die decoupling on core performance for the 0.18 micron version of the Pentium/spl reg/ 4 has been presented previously (T. Rahal-Arabi et al, VLSI Circ. Symp. Dig. of Tech. Papers, pp. 220-223, 2002). This paper complements the previous work by presenting the design and validation approach for the IO power supply of both the Pentium/spl reg/ III and Pentium/spl reg/ 4 processors. As the Pentium/spl reg/ III processor has separate IO and core supplies, it is a more suitable vehicle for the IO validation. The design approach relies on using the power supply impedance model to determine the required decoupling. The model is widely used in the design of high speed systems (A. Waizman and Chee-Yee Chung, IEEE Conf. Electrical Perf. of Electron. Packaging, pp. 65-68, 2000) but this paper shows that it is less adequate to evaluate performance. The validation approach consists of building several silicon wafers of the Pentium/spl reg/ III and Pentium/spl reg/ 4 processors with various amounts of decoupling. Extensive measurements are then conducted at the silicon, package, and system levels.

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A technique to calculate the relative on die power supply impedance of high power CMOS integrated circuits as a function of frequency is described. This approach uses the power supply current variation that is normally present in a microprocessor to stimulate the supply network, varying the clock rate of the processor in order to obtain multiple measurements. Using this technique the power supply impedance vs. frequency of a 0.18 /spl mu/m microprocessor was measured and compared to a simple lumped circuit model.

Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process

This paper describes a design methodology to determine the number of chip capacitors needed and its placement scheme for the latest Pentium/sup R/ III microprocessor package substrate for optimum performance. The effect of capacitors on the power supply and its performance and placement schemes are discussed and compared against measurements. Performance improvements are outlined and compared between the current 0.13 /spl mu/m and the previous 0.18 /spl mu/m silicon package technology designed for compatibility with existing systems.

High fan-in circuit design

The power delivery system of a recent IA32 microprocessor is described. The microprocessor takes advantage of voltage positioning and selects its own operating voltage dynamically to optimize performance while maintaining reliability. This capability is used by the processor to change its operating voltage and frequency during normal operation.

High performance package designs for a 1 GHz microprocessor

As Systems on Chip increase the portions of systems that are being integrated, the number and variety of analog/mixed signal circuits that are needed on a single chip are growing. At the same time, for reasons of cost, performance, and power the manufacturing of these nominally digital die is being scaled to ever smaller feature sizes. Unfortunately scaling to smaller devices does not deliver power or performance benefits for classical analog circuits. How are we going to bridge the gap between these two trends and keep Moores Law alive?

Reliability and performance tradeoffs in the design of on-chip power delivery and interconnects

This paper describes a 450 MHz multichip processor with a 2 MB, 3.6 GB/s level 2 cache. Chips are mounted on both sides of the substrate and use source synchronous, impedance controlled I/O circuits. Mixed voltages are used to allow each chip to take advantage of appropriate technology.