Alvar A. Dean

Challenges in clockgating for a low power ASIC methodology

Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activity in the logic modules as well as by eliminating power dissipation in the clock distribution network. There is an inherent pitfall though in implementing gating groups for hierarchical gated clock distribution because the groups are typically developed at the logic level with no information of the physical layout of the clocktree. Depending on the distribution of underlying sinks, maintaining gating groups can cause a wiring overhead that is potentially greater than the savings due to reduced switching. We look at modifications of zero-skew tree algorithms to consider both the physical and logical aspects of hierarchical gating. The algorithms are applied to data taken from a low power ASIC design. The best gated clocktree is created using both physical and logical information.

Multistack optimization for data-path chip layout

A special multistack structure and optimization technique to partition, place, and wire the data-path macros in the form of the multistack structure are described, taking into account the connectivity of all the chip logic (data path, control logic, chip drivers, on-chip memory). The overall objective is: to fit the circuits within the chip boundary; to ensure data-path internal wirability; as well as external stack wirability to the other circuits; and to minimize wire lengths for wirability and timing. A tool for automatic multistack optimization has been implemented and applied successfully to layout high-density data path chips. >

Multi-Stack Optimization for Data-Path Chip (Microprocessor) Layout

As data-path chips such as microprocessors and RISC chips become more complex, multiple stacks of data-path macros are required to implement the entire data-path. The physical decomposition of a chip into a single data-path stack, and control logic of random logic as in the past is not always feasible. This paper describes a special multi-stack structure, optimization techniques and algorithms to partition, place and wire the data-path macros in the form of the multi-stack structure, taking into account the connectivity of the entire chip logic (data-path, control logic, chip drivers, on-chip memory). The overall objective is: (1) to fit the circuits within the chip, (2) to ensure data-path wireability, including stack to random logic wireability, and (3) to minimize wire lengths for wireability and timing. A tool for automatic multi-stack optimization has been implemented and applied successfully to layout some high density data-path chips.

Low power methodology and design techniques for processor design

IBMs ASIC design methodologies is used to develop a low power microprocessor for the mobile (battery powered) marketplace. The design called for a reduction of active power by a factor of 10 times from an estimate of a product designed in a standard 3 volt ASIC design system. An overview of the design methodology and some of the innovative power reduction techniques are presented.

Multi-terrain partitioning and floor-planning for data-path chip (microprocessor) layout

A method is presented for floorplanning data-path chips by a technique of multi-terrain partitioning with integrated global wiring to partition the objects into terrains, followed by multistack placement and standard-cell placement. Requirements on terrain size, terrain shape, wirability, and timing are considered. Results obtained for some chip designs are presented.<<ETX>>

Low Power Design for ASIC Cores

A semicustom ASIC design methodology is used to develop a low power DSP core for mobile (battery powered) applications. Different low power design techniques are used, including dual voltage, low power library elements, accurate power reporting, pseudomicrocode, transition-once logic, clock gating, and others.

Partitioning and floor-planning for data-patch chip (microprocessor) layout

Data-path chips are typically made up different types of objects such as data-path macros, control logic cells (e.g. standard-cell), memory arrays, and off-chip drivers. Each type of object is quite different than the other type in terms of size, shape, wiring blockage, and pin location characteristics, so existing placement tools have difficulties in handling all the objects in a single step. This paper presents a hierarchical method to floor-plan, and then place and route data-path chips. A chip is divided into a number of regions (terrains) each reserved for objects of the same type. The objects are first partitioned into the different terrains, then the objects in the same type of terrains are placed using tool designed for that terrain characteristics. Physical partitioning, integrated with global wiring and timing control, partitions the objects into different terrains, multi-stack placement places the data-path macros, standard-cell placement places the random logic and off-chip drivers; then followed by detailed wiring. Requirements on terrain size, terrain shape, wirability and timing are all considered throughout the various stages of the physical design. Results obtained on some actual chip designs are also presented.