William R. Tonti

Reliability and design qualification of a sub-micron tungsten silicide E-Fuse

Sub micron CMOS features are attractive for Polysilicon Electrical Fuse (E-Fuse) repair options in VLSI designs. E-Fuse implementations as contrasted to laser fuses provide large density advantages over laser fusing and allows for the repair of packaged die, thus providing substantial final yield benefits. Laser fusing typically requires keep out design rules such that fuse neighbors are not unintentionally programmed from a misaligned laser source. Additionally laser fuses typically require a protective cavity to act as a programming debris reservoir. These reasons as well as improving upon the fuse repair solutions required to manage reliability and yield of large die [1] are the major driving forces for providing E-Fuse solutions. In this paper we describe a case study to optimize E-Fuse long term reliability. The methodology employed is for a Tungsten Silicide E-Fuse (WSi/sub 2/), but the intention of this paper is to benchmark a qualification plan that can be employed for any E-Fuse, i.e. polysilicon, metal, or anti-fuse qualification.

A fundamental performance limit of optimized 3.3-V sub-quarter-micrometer fully overlapped LDD MOSFET's

The direct experimental quantification of the relationship between gate-to-drain capacitance (C/sub gd/) and hot-electron reliability (HER) for fully overlapped LDD (FOLD) n-channel MOSFETs (NFETs) is reported. To broaden the applicability and achieve a wide range of FOLD finger lengths, the results are based on devices built using each of three different fabrication techniques. The experimentally observed tradeoff is compared to theoretical calculations to investigate its general and fundamental nature. It is shown that a peak in performance occurs at L/sub eff/ approximately=0.20 mu m for reliable 3.3-V NFETs with T/sub ox/=10 nm. Below 0.20 mu m, performance decreases due to the addition of the large FOLD fingers required to maintain adequate HER. This peak in performance can be shifted to L/sub eff/ approximately=0.15 mu m by introducing FOLD fingers only at the drain end of NFETs. For channel lengths greater than 0.25 mu m, the performances of 3.3-V FOLD NFETs and scaled 2.5-V single-diffusion NFETs are nearly equal. However, 2.5-V single-diffusion NFETs begin to offer a significant performance advantage over 3.3-V FOLD NFETs as channel lengths are reduced below 0.25 mu m. >

MOS Technology Drivers

The semiconductor industry has entered a new revolution where connectivity, applications, and an overall pervasive market drives the need for increased circuit density, improved performance, and a decrease in power dissipation. These issues are the backbone for some of the latest silicon technology advancements, including the integration of stress-enabled transistors and advanced silicon-on-insulator substrates. Future advancements may include multiple gated devices, high- gate oxides, and band-gap-tailored devices. This paper will review some of the early complementary metal-oxide-semiconductor transistor reliability issues and solutions that have allowed this industry to flourish over the last 25 years. A discussion on how these past issues and new advances affect power versus performance is the framework and motivation of this paper.

Impact of shallow trench isolation on reliability of buried- and surface-channel sub-/spl mu/m PFET

Shallow trench isolation exhibits all the required isolation-technology properties for ULSI. Its high degree of scaleability relies on the fact that its lateral (isolation width) and vertical (isolation depth) dimensions are decoupled due to an almost-ideal box-shape profile of the isolation. A consequence of the abrupt device edge is that a parasitic drain-to-source leakage path can exist at the corner and along the trench sidewall. This paper describes degradation mechanisms of surface-channel (SC) and buried-channel (BC) PFET devices that are directly related with a corner and sidewall parasitic leakage. Both parasitic regions show a characteristic degradation behavior that can limit device reliability for PFETs in the sub-/spl mu/m regime. The necessary processing conditions that overcome this limitation are also given.

Bias temperature reliability of n/sup +/ and p/sup +/ polysilicon gated NMOSFETs and PMOSFETs

A comparison of bias temperature reliability for submicron p/sup +/ and n/sup +/ polysilicon gated devices is presented. An instability associated with the p/sup +/ polysilicon gated devices that gives a negative Delta V/sub t/ and an interface-state buildup for positive bias temperature (+BT) was observed. This instability is explained in terms of the amount of the hydrogen-bonded component of moisture that remains in the gate electrode. It is further shown that a proper postmetallization anneal will significantly reduce this instability. Therefore, it is concluded that high BT reliability for p/sup +/ polysilicon gated devices can be achieved with process controls and actions that reduce the moisture in the device-active area. These controls provide an adequate reliability margin in dual work-function designs.<<ETX>>

Doping profile design for substrate hot carrier reliability in deep submicron field effect transistors

The authors explore the impact of substrate hot carrier emission on the design of submicron FETs. Performance requirements increase the vertical field for decreasing feature size in the deep submicron regime. This in turn significantly enhances the degradation sensitivity to substrate hot carriers. Models that support reliability data show the relationship between device stability, and the location of the peak channel doping concentration with respect to the Si-SiO/sub 2/ interface. It is well established that increased surface concentration alone has the effect of increasing the rate of substrate hot carrier emission due to higher surface fields. These results show that an optimum design tradeoff of the apparently conflicting requirements of device stability, off-current and performance can be achieved by proper choice of doping peak location when key process tolerances are accounted for.<<ETX>>

Long-term bias temperature reliability of P/sup +/ polysilicon gated FET devices

An instability was found to be associated with +BT stress for P/sup +/ poly-gated NMOSFETs (PNMOS) and PMOSFETs (PPMOS), but not with the N/sup +/ poly-gated devices (NNMOS and NPMOS). The instability with the P/sup +/ poly-gated devices, which is a decrease in threshold voltage (V/sub t/) and an increase in interface state density (D/sub it/), was significantly reduced following N/sub 2/ annealing at 400/spl deg/C. It is shown that adequate reliability for P/sup +/ poly-gated devices can be achieved for VLSI technologies. >

Device design methodology and reliability strategy for deep sub-micron technology [DRAMs]

This tutorial paper discusses device and process optimization techniques that may be employed in the design of current state-of-the-art bulk silicon DRAM technology. MOSFET performance and reliability issues are contrasted.