Ambrish Varma

Improving Behavioral IO Buffer Modeling Based on IBIS

High level behavioral modeling is widely used in lieu of low level transistor models to ascertain the behavior of input/output (IO) drivers and receivers. The input output buffer information specification (IBIS) is one of the most widely used methodologies to model IO drivers as it satisfies the basic requirements of a behavioral model such as IP protection, simple structure, fast simulation time, and reasonable accuracy. As driver technology gets increasingly complicated and rise time of input signal gets increasingly smaller, important considerations such as simultaneous switching noise (SSN) becomes a major consideration when simulating multiple IO drivers in the integrated circuit. Unfortunately, IBIS falls short of becoming a complete IO behavioral model when simulating for SSN. This paper addresses the problem by assessing what is missing in IBIS. A method is presented for compensating for the missing information by complimenting the IBIS model with a black box that is simulator independent, without compromising with the speed that IBIS enjoys over the transistor models.

The development of a macro-modeling tool to develop IBIS models

A tool to convert SPICE netlists to IBIS (Input/Output Buffer Information Specification) models is presented. This tool simulates the netlist on a user-desirable SPICE engine and produces both static and dynamic characteristics of the IBIS model.

Simultaneous switching noise in IBIS models

In this paper, a tool to convert SPICE netlists to IBIS (Input/Output Buffer Information Specification) models is presented This tool simulates the netlist on a user-desirable SPICE engine and produces both static and dynamic characteristics of the IBIS model. A CMOS driver circuit is simulated in HSPICE and compared with an equivalent circuit created with IBIS models of the same drivers. Outputs from the drivers are compared IBIS models are also compared against macro-models of nonlinear digital drivers using spline functions with finite time difference approximation modeling techniques.

SSN issues with IBIS models

A CMOS driver circuit is simulated in HSPICE and compared with an equivalent circuit created with IBIS (input/output buffer information specification) models of the same drivers. The IBIS models are created using the s2ibis tool from North Carolina State University. IBIS model of the driver is also compared against model created using spline functions with finite time difference approximation modeling techniques. The three modeling techniques are analyzed for accuracy in modeling simultaneous switching noise in drivers.

A new method to achieve improved accuracy with IBIS models

IBIS (input/output buffer information specification) models are known to lack information regarding power and ground bounce resulting in incorrect simulations. In this paper, a novel solution to the problem is proposed making it possible to simulate IBIS models with available simulators and have a realistic chance at simulating simultaneous switching noise (SSN) that are present in most if not all high speed circuits. To demonstrate the solution, a CMOS voltage-mode driver circuit and a current-mode LVDS driver circuit are simulated using HSPICE and compared with equivalent circuits created with IBIS models of the same drivers. The IBIS models are created using the s2ibis tool from North Carolina State University.

Developing Improved IO Buffer Behavioral Modeling Methodology Based on IBIS

A new macromodeling methodology based on IBIS (input/output buffer information specification) models is proposed. IBIS models are known to lack information regarding power and ground bounce (Varma, et. al., 2004 and Yang, et. al., 2005) resulting in incorrect system level simulations. The new macromodel works with available simulators and produces models that can be simulated accurately for simultaneous switching noise (SSN). To demonstrate the solution, a CMOS voltage-mode driver circuit and a MICRON DDR2 driver are simulated using HSPICE and compared with equivalent circuits created with IBIS models of the same drivers

CAD flows for chip-package coverification

A unified method is presented for layout and package design implemented within a commercial design environment that will reduce design time and enable chip-package coverification

CAD flows for chip-package codesign

A unified method is presented for layout and package design implemented within a commercial design environment that will reduce design time and enable chip-package codesign.

High-speed bus signal integrity compliance using a frequency-domain model

A new technique for frequency-domain compliance testing of high-speed differential interfaces is implemented in a signal integrity simulation tool that can accurately predict a channels bit-error rate (BER) from seven frequency-domain parameters. This greatly increases the speed and efficiency of designing the number of computer systems required for custom configurations in scale-out data centers. The compliance method is tested with three example case studies in channel printed circuit board (PCB) design. These three studies are: finding maximum loss due to routable trace length as a function of wiring depth layer (which affects crosstalk), finding the maximum routable length when introducing reflections and crosstalk due to adding a connector in the channel, and finding what amount of skew introduced by asymmetry in a differential pair for reasons such as the glass weave or different copper lengths under which a channel can still operate. The pass/fail frequency compliance results are discussed and compared with the time-domain simulation results of the channels tested.

IBIS Simulation Using the Latency Insertion Method (LIM)

This paper presents an approach for the transient simulation of I/O buffers described by IBIS models. Using the latency insertion method, a formulation can be obtained for the transient behavior of IBIS models combined with external circuitry. The formulation offers better convergence than traditional Newton-Raphson methods and is therefore more robust. The method also implements the BIRD95 and BIRD98 updates that account for predriver current, simultaneous switching noise, and gate modulation effects. Several computer simulations are performed to validate the method.