Glen A. Wiedemeier

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking

POWER8™ is a 12-core processor fabricated in IBMs 22 nm SOI technology with core and cache improvements driven by big data applications, providing 2.5× socket performance over POWER7+™. Core throughput is supported by 7.6 Tb/s of off-chip I/O bandwidth which is provided by three primary interfaces, including two new variants of Elastic Interface as well as embedded PCI Gen-3. Power efficiency is improved with several techniques. An on-chip controller based on an embedded PowerPC™ 405 processor applies per-core DVFS by adjusting DPLLs and fully integrated voltage regulators. Each voltage regulator is a highly distributed system of digitally controlled microregulators, which achieves a peak power efficiency of 90.5%. A wide frequency range resonant clock design is used in 13 clock meshes and demonstrates a minimum power savings of 4%. Power and delay efficiency is achieved through the use of pulsed-clock latches, which require statistical validation to ensure robust yield.

A frequency-domain high-speed bus signal integrity compliance model: Design methodology and implementation

This paper investigates channel/link frequency domain compliance in order to predict compatibility with a buss chip I/O circuitry at its ends. Any channel can be associated with certain frequency domain parameter values which are easily calculated from the channel S-parameter matrix. A set of frequency domain parameters that can sufficiently describe a channel are defined in this paper. Using a genetic algorithm, the frequency domain parameter bounds in a multidimensional space describing PCIe-Gen3 (bus speed = 8 Gb/s) compliant channels are found. Details of the methodology used in order to arrive at the multidimensional frequency domain compliance model, model results and model simulation validation testing are presented.

High-speed bus signal integrity compliance using a frequency-domain model

A new technique for frequency-domain compliance testing of high-speed differential interfaces is implemented in a signal integrity simulation tool that can accurately predict a channels bit-error rate (BER) from seven frequency-domain parameters. This greatly increases the speed and efficiency of designing the number of computer systems required for custom configurations in scale-out data centers. The compliance method is tested with three example case studies in channel printed circuit board (PCB) design. These three studies are: finding maximum loss due to routable trace length as a function of wiring depth layer (which affects crosstalk), finding the maximum routable length when introducing reflections and crosstalk due to adding a connector in the channel, and finding what amount of skew introduced by asymmetry in a differential pair for reasons such as the glass weave or different copper lengths under which a channel can still operate. The pass/fail frequency compliance results are discussed and compared with the time-domain simulation results of the channels tested.

Package and Printed Circuit Board Design of a 19.2 Gb/s Data Link for High-Performance Computing

A 19.2 Gb/s per lane link with IBMs latest POWER8 processor module has been analyzed. This paper presents the overview of the high-speed link design from the signal integrity point of view. Design approaches in package and printed circuit board (PCB) to support the target data-rate have been discussed. The end-to-end communication bus is modeled from extracted post-route design with a 3-D full-wave extractor and has been simulated with IO properties at system level. Bath-tub curves are generated from data gathered in functioning systems running this 19.2 Gb/s link to confirm the operation of the link meets the required bit-error-rate criteria as the modeling and simulation predicted.