Alan Glaser

The development of a macro-modeling tool to develop IBIS models

A tool to convert SPICE netlists to IBIS (Input/Output Buffer Information Specification) models is presented. This tool simulates the netlist on a user-desirable SPICE engine and produces both static and dynamic characteristics of the IBIS model.

Simultaneous switching noise in IBIS models

In this paper, a tool to convert SPICE netlists to IBIS (Input/Output Buffer Information Specification) models is presented This tool simulates the netlist on a user-desirable SPICE engine and produces both static and dynamic characteristics of the IBIS model. A CMOS driver circuit is simulated in HSPICE and compared with an equivalent circuit created with IBIS models of the same drivers. Outputs from the drivers are compared IBIS models are also compared against macro-models of nonlinear digital drivers using spline functions with finite time difference approximation modeling techniques.

Issues in partitioning integrated circuits for MCM-D/flip-chip technology

In order to successfully partition a high performance large monolithic chip onto MCM-D/flip-chip-solder-bump technology, a number of key issues must be addressed. These include the following: (1) Partitioning a single clock-cycle path across the chip boundary within using; (2) Ability to use off-the-shelf memories; (3) Using the MCM for power, ground, and clock distribution; and (4) Managing test costs. This paper presents a discussion on these issues, using a CPU as an example, and speculates on some interesting possibilities arising from partitioning.

A flip-chip implementation of the Data Encryption Standard (DES)

We describe a flip-chip MCM-D implementation of a Data Encryption Standard (DES) engine. Novel features include the following: use of dense area-array I/O to achieve high bandwidth, fully-pipelined architecture which supports multiple encryptions (e.g., triple DES) with no loss of throughput; ability to multiplex datastreams, each under the control of a potentially unique key, and use of the MCM-D substrate to distribute power, ground and clock signals. The chip is being fabricated in a 0.6 /spl mu/m CMOS process, while the MCM is being built in a 4-layer polyimide MCM-D process. Circuit simulations indicate the device will operate with a throughput of 9.6 Gb/s.

Flip-chip power distribution

By using thin-film (MCM-D) and flip-chip solder bump technologies to distribute power and ground to an IC, the percentage of metal fill required on the power and ground layers can be reduced. However, significant reductions require a very dense solder bump technology.

A method for on-chip interconnect characterization

We present and novel method for the measurement of interconnect capacitance, atomic capacitance microscopy. We also present VLSI structures which allow correlation of ACM and traditional (VNA, TDR, direct capacitance) measurement techniques.

CAD flows for chip-package coverification

A unified method is presented for layout and package design implemented within a commercial design environment that will reduce design time and enable chip-package coverification

CAD flows for chip-package codesign

A unified method is presented for layout and package design implemented within a commercial design environment that will reduce design time and enable chip-package codesign.

Infrastructure and course progression for complex IC design education

The ability to cope with design complexity is an important skill for computer engineers, especially potential system on a chip design engineers. Complexity has many facets, including gate count, the ability to handle multiple disciplines simultaneously, and the ability to cope with complex CAD tools. Teaching complexity also requires considerable investment in tool flows, design examples and tutorials. Here, the approach used at North Carolina State University, USA, is described and illustrated.

Issues in chip-package codesign with MCM-D/flip-chip technology

By distributing on-chip global power, ground, and clock planes on a thin film MCM, the IC can be made smaller, faster, and less noisy while consuming less power. These advantages are demonstrated by a number of case studies: two demonstrator ICs and an analysis of the DEC Alpha 21264 clock distribution scheme. However, there are a number of practical issues that need to be addressed, including process variations and test. In this paper, we present the case studies and a treatment of these practical issues.