Amin Hamidian

Cooperative Indoor Localization Using 24-GHz CMOS Radar Transceivers

This paper presents the first truly wireless 24-GHz round-trip time-of-flight local positioning frontend with an integrated CMOS transceiver. The transceiver in 130-nm CMOS technology features a novel receiver/transceiver switching concept, which reduces RF losses between the receiver/transmitter and antenna and drastically improves the transmit/receive isolation. The low-power RF transceiver chip was integrated with a digital signal-processing unit and mounted on a circuit board to form a system-level demonstrator of a secondary radar node incorporating synchronization and a distributed localization algorithm. The performance of the self-organizing localization network is evaluated in an indoor setup using comparisons with reference trajectories. Experimental results show a distance precision between the active nodes close to the theoretical optimum that can be achieved with the used signal parameters, as well as an absolute localization error in the centimeter range.

Extraction of RF feeding structures for accurate device modeling up to 100 GHz

This paper presents the extraction techniques of the RF feeding structures for accurate modeling of on-chip passive and active components. The presented techniques have been applied for a group of test structures realized in a 90 nm CMOS process and validated through measurements up to 100 GHz. Feeding structures comprising RF probing pads, pad to the transmission line transition and short 50 Ω transmission lines have been modeled with the help of measurements and electromagnetic simulations. The modeled structures have been utilized in the extraction of the test components like MIM capacitors, transistors etc., from the measurements. The comparisons between the foundry based models and the extracted results of the components show a good accuracy validating the applied techniques up to 100 GHz operating frequencies.

24 GHz CMOS transceiver with novel T/R switching concept for indoor localization

This paper presents a 130 nm CMOS transceiver for 24 GHz wireless indoor localization. Due to a novel Rx/Tx switching concept RF-losses between receiver/transmitter and antenna could be reduced and the T/R isolation was drastically improved. The measured transceiver chip achieves an output power and noise figure of >5 dBm and <;6 dB, respectively with 2 mm2 total chip size. The complete transceiver consumes 16 mW in the Rxand 26 mW in the Tx-mode. The RF-transceiver-chip was integrated with a DSP-unit and mounted on a PCB for wireless indoor localization demonstration. The measured results show a distance measurement precision in the cm-range.

60 GHz wide-band power amplifier

This paper presents a fully integrated 60 GHz single stage power amplifier with cascode topology. The PA is designed on 0.25 µm SiGe:C BiCMOS technology. The technology provides ft and fmax ≈ 200 GHz. The PA has achieved the 1dB gain bandwidth of more than 9 GHz from 57 GHz to 66 GHz and 3dB gain bandwidth of more than 18 GHz (30 %) from 51 GHz to 69 GHz. The PA has been designed to have the wideband large and small signal gain in the whole range. This has resulted to 1dB gain compression point more than 11.5 dBm and power added efficiency better than 9 % from 57 GHz to 65 GHz. The PA achieves the maximum P1dB of 13.5 dBm at around 58 GHz. The constant gain, high linearity and good PAE for the whole range (57 to 66 GHz) has made this power amplifier quite interesting for 60 GHz applications.

60 GHz power amplifier utilizing 90 nm CMOS technology

This paper presents a fully integrated 60 GHz two stage power amplifier for wireless applications using common source topology and power combining. The PA is implemented in a 90 nm low power CMOS technology. The output power of the amplifier has been improved with the help of Wilkinson power combining technique. Also the Wilkinson power combiner has been utilized as a part of input and output matching networks to match the 16 Ω at the terminals of the power amplifier to 50 Ω at the output of the Wilkinson network. At 60 GHz the power amplifier achieves 11 dBm saturation output power, 9 dBm output power at 1dB gain compression point and more than 8 dB small signal gain with a peak power added efficiency of 6%. The broadband performance of the gain has been achieved utilizing the cascaded structures. The matching networks are based on high quality factor shielded coplanar transmission lines and fixed 300 fF MIM-capacitors. The detailed design procedure and the achieved measurement results are presented in this work.

Coplanar transmission lines on silicon substrates for the mm-wave applications

This work investigates the design of two different coplanar transmission lines and their application at millimeter wave frequencies up to 100 GHz. The coplanar structure has been selected to improve the grounding and also to remove the effect of the fillers on the transmission line. The two transmission lines differ by their bottom metal layer pattern. In the first transmission line the bottom metal is solid ground while in the second transmission line the bottom metal layer is used as a shield. The transmission lines are optimized for different parameters like insertion loss, inductance per unit length and size. Also to justify the electromagnetic simulated models of the transmission lines, different transmission lines have been realized and measured. The characteristics of the transmission lines are extracted from the measurement results. Comparison of the model and the measured results shows a good agreement up to 100 GHz. Finally, two 60 GHz amplifiers in 90 nm CMOS technology were designed based on these transmission lines.

45 GHz low power static frequency divider in 90 nm CMOS

This work presents the design of a Q-band static frequency divider with quadrature signal output suitable for 60 GHz application. The RF performance improvement and power consumption reduction is achieved by using inductive peaking, resistor splitting techniques as well as proper transistor sizing. The static frequency divider is realized in a 90 nm CMOS technology with a chip area of 0.60×0.75 mm2. The self-oscillation frequency is 20.5 GHz with 12 GHz locking range. -16 dBm output power with less than -1 dBm input sensitivity were measured. The static frequency divider core and the output buffers consume 6.9 mW and 1.2 mW respectively from a 1.2 V power supply.

Device characterization in 90 nm CMOS up to 110 GHz

This paper presents the small signal characterization of nMOS transistors in 90 nm CMOS technology. Two different transistor widths are characterized based on the measurement results up to 110 GHz. The widths of the transistors are optimized for low noise and power amplifier applications at 60 GHz. For the characterization purpose, the on-chip feeding structures (pads, transmission lines and vias) are extracted from the measurement results with the help of Electro Magnetic simulations.

High power V-band power amplifier

This paper presents a fully integrated V-band two stage power amplifier with cascode topology. The PA is designed on 0.25 µm SiGe:C BiCMOS technology. The technology provides ft and fmax ≈ 200 GHz. The two stage PA provides a gain of 17 dB at 64 GHz. The PA has been optimized for biasing circuit, PA Core and the matching networks. This has resulted in high power and high linearity from 58 GHz to 66 GHz. As a result of the optimization the 1 dB gain compression point remains better than 12 dBm in the entire range of the frequency. The PA achieves the maximum P1dB of 13.8 dBm at around 64 GHz.

A High Performance and Fully Differential V-Band CMOS Transmitter

This work presents the design of high performance components and their integration into a fully differential 60 GHz transmitter on 90 nm CMOS technology. The design is optimized to cover all four channels of the IEEE 802.11ad standard. Further, the effects of fully differential topology and transformer based design on different aspects of the transmitter performance are discussed. The measured results of the transmitter show average values of around 25 dB conversion gain, 15 dBm saturated output power, 13 dBm output power at 1dB compression point and -92 dBc/Hz phase noise at 1 MHz offset for all channels with a total chip size of 3.8 mm2.