Amit Sehgal

Physics based threshold voltage extraction and simulation for poly-crystalline thin film transistors using a double-gate structure

In this work, a two-dimensional potential distribution formulation/model is presented for double-gate poly-crystalline silicon thin film transistors. The work aims at deriving a potential solution for the threshold voltage estimation of the device under consideration. The Greens function approach is adopted for the two-dimensional potential solution. The developed formulation incorporates the effects due to traps and grain boundaries. The existence of short-channel effects and drain-induced barrier-lowering effects can also be seen from the characteristics. A relation to achieve the targeted threshold voltage with the physical gate dielectric thickness, dielectric constant, substrate doping concentration, grain size and drain–source voltage as parameters is also presented. The model is then extended to evaluate drain current performance. The results obtained show an excellent agreement with numerical modelling based on the finite difference method and also a good agreement with simulation results, thus demonstrating the validity of our model.

Poly-crystalline Silicon Thin Film Transistor: a Two- dimensional Threshold Voltage Analysis using Green's Function Approach

A two?dimensional treatment of the potential distribution under the depletion approximation is presented for poly?crystalline silicon thin film transistors. Green’s function approach is adopted to solve the two?dimensional Poisson’s equation. The solution for the potential distribution is derived using Neumann’s boundary condition at the silicon?silicon di?oxide interface. The developed model gives insight into device behavior due to the effects of traps and grain?boundaries. Also short?channel effects and drain induced barrier lowering effects are incorporated in the model. The potential distribution and electric field variation with various device parameters is shown. An analysis of threshold voltage is also presented. The results obtained show good agreement with simulated results and numerical modeling based on the finite difference method, thus demonstrating the validity of our model.

Modeling Aspects of Sub-100-nm MOSFETs for ULSI-Device Applications

Ultrathin oxides (1-3 nm) are foreseen to be used as gate dielectric in complementary-MOS technology during the next ten years. Nevertheless, they require new approaches in modeling and characterization due to the onset of quantum effects. Predicting device characteristics including quantum effects requires solving of Schroumldingers equation together with Poissons equation. In this paper, Poissons equation is solved in two dimensions (2-D) over the entire device using Greens function approach, while Schroumldingers equation is decoupled using triangular-potential-well approximation. The carrier density thus obtained is included in the space-charge density of Poissons equation to obtain quantum-carrier confinement effects in the modeling of sub-100-nm MOSFETs. The framework also consists of the effects of source/drain-junction curvature and depth, short-channel effects, and drain-induced barrier-lowering effect. The 2-D potential profiles thus obtained with above said effects form the basis for an estimation of threshold voltage. Using this potential distribution, the transfer characteristics of the device are also evaluated. The method presented is comprehensive in the treatment, as it neither requires self-consistent numerical modeling nor it contain any empirical or fitting expression/parameter to provide formulation for quantized-carrier effect in the inversion layer of MOSFETs. The results obtained show good agreement with available results in the literature and with simulated results, thus proving the validity of our model

Modelling challenges in sub-100 nm gate stack MOSFETs

The aim of this work is to present a two-dimensional analysis for different gate stack dielectric structured n-MOSFETs with carrier quantization effects. The model is developed using Greens function for solving Poissons equation, without implying the extensive effort required for a fully self-consistent solution of the Schrodinger and Poisson equations. Explicit results for potential distribution, threshold voltage and drain current, with different structural and bias parameters, have been presented, typical in the operation of modern devices. The model includes short channel, drain bias, and junction curvature effects. Based on extensive simulation and developed formulation, it is found that the conventional concept of a scaled transformation method for gate stack structures to replace silicon-dioxide (SiO2) dielectric thickness with a thicker high dielectric does not predict the same characteristics. It has also been shown that using double-layer gate stack structures with low-k dielectric as the spacer material can well confine the electric fields within the channel, thereby enhancing gate controllability on the channel charge. Comparison of the results thus obtained is done with simulated results to justify the analysis.

Analytical modelling of the kink regime of a short channel polycrystalline silicon thin film transistor

An analytical model for the post-saturation region including the kink regime of a short channel polycrystalline silicon thin film transistor is presented. Considering the impact ionization mechanism caused by high electric field in the pinch off region near the drain, an expression for the channel potential is developed. The avalanche multiplication factor, an important parameter monitoring the impact ionization phenomenon is determined and discussed. Further, an expression for the drain-source current in the kink regime is determined and studied. The dependence of the kink current on the channel length and grain size is investigated. The results so obtained are compared with experimental data and an excellent match verifies the proposed model.