Ritesh Gupta

Dual-Material Double-Gate SOI n-MOSFET: Gate Misalignment Analysis

The dual-material double-gate (DMDG) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) is the leading contender for sub-100-nm devices because it utilizes the benefits of both double-gate and dual-material-gate structures. One major issue of concern in the DMDG-MOSFET is the alignment between the top and the bottom gate that critically influences the device performance. In this paper, we have investigated the effects of gate misalignment in the DMDG SOI n-MOSFET. In this regard, analytical modeling and extensive simulations have been carried out to analyze the gate misalignment effects on device performance like surface potential, electric field, threshold voltage, subthreshold slope, drain-induced barrier lowering, drain current, and transconductance. Considering the fact that gate misalignment can occur on any side of the gate, both source- and drain-side misalignments have been discussed. Analytical and simulated results are found to be in good agreement, which authenticate our proposed model for the DMDG structure.

Analytical two-dimensional modeling for potential distribution and threshold voltage of the short-channel fully depleted SOI (silicon-on-insulator) MOSFET

Abstract A two-dimensional analytical model for fully depleted SOI MOSFETs is presented. An extensive study of potential distribution in the silicon film is carried out for non-uniform doping distribution and extended to find an expression for threshold voltage in the sub micrometer region. The results so obtained are verified with experimental data. The present model calculates a critical gate voltage (for short channel fully depleted SOI devices) beyond which gate losses its control on drain current. The advantages of SOI MOSFETs over the bulk counterparts are explained on the basis of drain induced barrier lowering [DIBL]. It is also shown that the threshold voltage for the thin film SOI MOSFET is less than that of bulk MOSFET. The short-channel effects, DIBL and threshold voltage reduction, are well predicted in the present model.

Short Channel Analytical Model for High Electron Mobility Transistor to Obtain Higher Cut-Off Frequency Maintaining the Reliability of the Device

A comprehensive short channel analytical model has been proposed for High Electron Mobility Transistor (HEMT) to obtain higher cut-off frequency maintaining the reliability of the device. The model has been proposed to consider generalized doping variation in the directions perpendicular to and along the channel. The effect of field plates and different gate-insulator geometry (Tgate, etc) have been considered by dividing the area between gate and the high band gap semiconductor into different regions along the channel having different insulator and metal combinations of different thicknesses and work function with the possibility that metal is in direct contact with the high band gap semiconductor. The variation obtained by gate-insulator geometry and field plates in the field and channel potential can be produced by varying doping concentration, metal workfunction and gate-stack structures along the channel. The results so obtained for normal device structure have been compared with previous proposed model and numerical method (finite difference method) to prove the validity of the model.

Numerical Model of Gate-All-Around MOSFET With Vacuum Gate Dielectric for Biomolecule Detection

In this letter, a dielectric-modulated GAA MOSFET with vacuum gate dielectric is proposed for enhanced sensitivity for label-free detection of neutral and charged biomolecules. We developed an analytical model to model the response of GAA MOSFET in the presence of biomolecules. The model is verified with simulation results of ATLAS-3-D. Results indicate that GAA MOSFET biosensor with vacuum gate dielectric is able to serve as a highly sensitive low-power label-free biosensor along with advantages of robustness, reliability, and CMOS compatibility.

An analytical parasitic resistance dependent I d - V d model for planar doped InA1As/InGaAs/InP HEMT using non-linear charge control analysis

An analytical parasitic resistance dependent model for the current voltage characteristics for InAlAs/InGaAs/ InP HEMT is proposed. The model uses a new polynomial dependence of sheet carrier concentration on gate voltage to calculate Id-Vd characteristics and has been extended to obtain transconductance, output conductance and cut-off frequency of the device. A maximum cut-off frequency of 83 and 175 GHz was obtained for channel length of 0.25 and 0.1 µm, respectively. Close agreement with published results confirms the validity of our approach.

Graded channel architecture: the solution for misaligned DG FD SOI n-MOSFETs

A double-gate (DG) metal-oxide semiconductor field-effect transistor (MOSFET) is the leading contender for a deep submicron MOSFET to reduce gate oxide tunneling. One major issue of concern in a DG-MOSFET is the alignment between the top and bottom gates that influences the device performance, especially in a subthreshold regime. Use of graded channel (high–low, low–high and low–high–low doping) architecture somehow reduces this gate misalignment effect and hence has been analyzed in the present paper through intensive simulation and analytical analysis. The model uses the conformal mapping transformation approach to include the fringing field effect that arises at the bottom gate electrode in the ungated region and is used to predict the surface potential, electric field, threshold voltage, sub-threshold slope and drain-induced barrier lowering effects. The results so obtained have been verified with 3D numerical simulation using an ATLAS 3D device simulator.

Metal Insulator Gate Geometric HEMT: Novel Attributes and Design Consideration for High Speed Analog Applications

Improvement in breakdown voltage (BVds) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length (L g ), but due to lithographic limitation, shortening L g below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate on to the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the BVds of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in BV ds can be obtained by applying field plates, especially at the drain side. The important parameters affecting BVds and cut-off frequency (f T ) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, Γ-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.

An analytical model for discretized doped InAlAs/InGaAs heterojunction HEMT for higher cut-off frequency and reliability

Abstract In the proposed work the model has been formulated for discretized doped HEMT, where the conventional uniformly doped, pulsed doped and delta doped structure are the special cases. An expression for sheet carrier density has been formulated considering the effect of doping-thickness product and has been extended to calculate drain current, transconductance, capacitance and cut-off frequency of the device. The model also takes into account the non-linear relationship between sheet carrier density and quasi Fermi energy level to validate it from subthreshold region to high conduction region. The results so obtained have been compared with pulsed doped structure to validate the model. The analysis concentrates on the distance of doping from the heterojunction and gate electrode. Different design criteria have been given to dope the carriers (amount and distance) in different regions to optimize the performance for higher sheet carrier density/parallel conduction voltage/effective parallel conduction voltage ( V c −V off ) to increase the transconductance, cut-off frequency and reliability of the device.

An analytical model for turn-on characteristics of short channel polycrystalline-silicon thin-film transistor for circuit simulation

Short channel effects are incorporated to investigate the impact of the channel length on the turn-on characteristics of a polycrystalline silicon thin-film transistor (poly-Si TFT). The developed threshold voltage and field effect mobility are the key parameters in analysing the above-threshold characteristics. The expressions for the device transconductance and drain conductance are then developed, from which the channel resistance has also been extracted. The expressions so developed are simple and can be extensively used in modeling the short channel TFT. The predicted results are compared with available experimental data, and excellent matching confirms the validity of the model.

Modeling of short geometry polycrystalline-silicon thin-film transistor

An accurate model for the device characteristics of a short geometry polysilicon thin-film transistor (poly-Si TFT) is developed. The proposed channel length dependent threshold voltage and the current-voltage (I-V) characteristics determined are in excellent agreement with experimental results confirming the validity of this model. The impact of the grain size on device characteristics is also shown.