Amyn Poonawala

Simultaneous source-mask optimization: a numerical combining method

A new method for simultaneous Source-Mask Optimization (SMO) is presented. In order to produce optimum imaging fidelity with respect to exposure lattitude, depth of focus (DoF) and mask error enhancement factor (MEEF) the presented method aims to leverage both, the available degrees of freedom of a pixelated source and those available for the mask layout. The approach described in this paper is designed as to work with dissected mask polygons. The dissection of the mask patterns is to be performed in advance (before SMO) with the Synopsys Proteus OPC engine, providing the available degrees of freedom for mask pattern optimization. This is similar to mask optimization done for optical proximity correction (OPC). Additionally, however, the illumination source will be simultaneously optimized. The SMO approach borrows many of the performance enhancement methods of OPC software for mask correction, but is especially designed as to simultaneously optimize a pixelated source shape as nowadays available in production environments. Designed as a numerical optimization approach the method is able to assess in acceptable times several hundreds of thousands source-mask combinations for small, critical layout snippets. This allows a global optimization scheme to be applied to the SMO problem which is expected to better explore the optimization space and thus to yield an improved solution quality compared to local optimizations methods. The method is applied to an example system for investigating the impact of source constraints on the SMO results. Also, it is investigated how well possibly conflicting goals of low MEEF and large DoF can be balanced.

Model-based assist feature placement using inverse imaging approach

The continuing reduction in feature dimensions and tightening of process constraints have led to an increasing demand for model-based approaches, which can efficiently explore the AF solution space, and achieve AF configurations not easily accessible via rules. In this work, we approach the AF placement problem as an inverse imaging problem. We discuss the generation of an inverse mask field and its use in determining the assist feature location. The results are compared with the single iteration intensity-field based AF placement with regard to symmetry, speed, memory, convergence, and accuracy. Several results with different pitches and illumination conditions are presented to demonstrate the robustness and adaptability of the inverse mask AF placement.

Source Mask Optimization for Advanced Lithography Nodes

Source mask optimization is becoming increasingly important for advanced lithography nodes. In this paper, we present several source mask optimization flows, with increasing levels of complexity. The first flow deals with parametric source shapes. Here, for every candidate source, we start by placing model-based assist features using inverse mask technology (IMT). We then perform a co-optimization of the main feature (for OPC) and assist feature (for printability). Finally, we do a statistical analysis of several lithography process metrics to determine the quality of the solution, which can be used as feedback to determine the next candidate source. In the second flow, the parametric source is instead approximated by a pixel based source inverter, providing a fast and efficient way of exploring the source solution space. The final flow consists of pixilated source shapes realizable via DOEs or programmable illumination.

Integrating assist feature print fixing with OPC

A challenge in model-based assist feature placement is to find optimal placements while satisfying mask rules and preventing AF printing. There are numerous strategies for achieving this ranging from fully rule-based methods to pixel-based inversion. Our proposed solution is to identify the optimal locations of assist features using modeling information based strictly on optics and resist stack optical characteristics. Once these positions have been found, preliminary AFs can be placed. At this point suggested sizes and shapes can be identified, although these can later be modified. In a later step, MRC cleanup, printability fixing, and main-pattern OPC can be performed simultaneously. This has the advantage of allowing the use of the full process model to predict the location of OPC edges accurately, and use calibrated or 3d mask models to determine assist feature printing behavior. This correction is done while maintaining MRC constraints. In this flow, an AF placement field, generated from the pre-OPC target patterns, can be used to provide accurate guidance on how to move assist features to get the most benefit while keeping other constraints in mind. Using this method, a range of printability fixing strategies, guided by placement benefits, is available. We present data showing that the benefit of AF placements can be determined from optical parameters, on target (non-OPC) data, and that this method leads to beneficial yet compliant masks.

Suppressing ringing effects from very strong off-axis illumination with novel OPC approaches for low k1 lithography

With the delay in commercialization of EUV and the abandonment of high index immersion, Fabs are trying to put half nodes into production by pushing the k1 factor of the existing scanner tool base as low as possible. A main technique for lowering lithographic k1 factor is by moving to very strong offaxis illumination (i.e., illumination with high outer sigma and a narrow range of illumination angles), such as Quadrapole (e.g., C-Quad), custom or even dipole illumination schemes. OPC has generally succeeded to date with either rules-based or simple model-based dissection together with target point placement schemes. Very strong off-axis illumination, however, creates pronounced ringing effects on 2D layout and this makes these simpler dissection techniques problematic. In particular, it is hard to prevent overshoot of the contour around corners while simultaneously dampening out the ringing further down the feature length. In principle, a sufficiently complex set of rules could be defined to solve this issue, but in practice this starts to become un-manageable as the time needed to generate a usable recipe becomes too long. Previous implementations of inverse lithography demonstrated that good CD control is possible, but at the expense of the mask costs and other mask synthesis complications/limitations. This paper first analyzes the phenomenon of ringing and the limitations seen with existing simpler target placement techniques. Then, different methods of compensation are discussed. Finally, some encouraging results are shown with new traditional and inverse experimental techniques that the authors have investigated, some of which only demand incremental changes to the existing OPC framework. The results show that new OPC techniques can be used to enable successful use of very strong off-axis illumination conditions in many cases, to further reduce lithographic k1 limits.

Model-based assist feature placement for 32nm and 22nm technology nodes using inverse mask technology

Inverse imaging has been long known to provide a true mathematical solution to the mask design problem. However, it is often times marred by problems like high run-time, mask manufacturability costs, and non-invertible models. In this paper, we propose a mask synthesis flow for advanced lithography nodes, which capitalizes on the inverse mask solution while still overcoming all the above problems. Our technique uses inverse mask technology (IMT) to calculate an inverse mask field containing all the useful information about the AF solution. This field is fed to a polygon placement algorithm to obtain initial AF placements, which are then cooptimized with the main features during an OPC/AF print-fix routine to obtain the final mask solution. The proposed flow enables process window maximization via IMT while guaranteeing fully MRC compliant masks. We present several results demonstrating the superiority of this approach. We also compare our IMT-AFs with the best AF solution obtained using extensive brute-force search (via a first principles simulator, S-litho), and prove that our solution is optimum.

Rigorous ILT optimization for advanced patterning and design-process co-optimization

Despite the large difficulties involved in extending 193i multiple patterning and the slow ramp of EUV lithography to full manufacturing readiness, the pace of development for new technology node variations has been accelerating. Multiple new variations of new and existing technology nodes have been introduced for a range of device applications; each variation with at least a few new process integration methods, layout constructs and/or design rules. This had led to a strong increase in the demand for predictive technology tools which can be used to quickly guide important patterning and design co-optimization decisions. In this paper, we introduce a novel hybrid predictive patterning method combining two patterning technologies which have each individually been widely used for process tuning, mask correction and process-design cooptimization. These technologies are rigorous lithography simulation and inverse lithography technology (ILT). Rigorous lithography simulation has been extensively used for process development/tuning, lithography tool user setup, photoresist hot-spot detection, photoresist-etch interaction analysis, lithography-TCAD interactions/sensitivities, source optimization and basic lithography design rule exploration. ILT has been extensively used in a range of lithographic areas including logic hot-spot fixing, memory layout correction, dense memory cell optimization, assist feature (AF) optimization, source optimization, complex patterning design rules and design-technology co-optimization (DTCO). The combined optimization capability of these two technologies will therefore have a wide range of useful applications. We investigate the benefits of the new functionality for a few of these advanced applications including correction for photoresist top loss and resist scumming hotspots.

Addressing optical proximity correction challenges from highly nonlinear models

Model-based optical proximity correction (MB-OPC) has been widely applied in advanced lithography processes today. As k1 factor decreases and circuit design complexity increases, various advanced OPC modeling techniques have been employed to better simulate the lithography processes, such as mask3D (M3D), negative tone development (NTD) modeling techniques, etc. These advanced OPC modeling techniques introduce increasingly nonlinear behaviors in MB-OPC and bring many challenges in controlling edge placement error (EPE) and critical dimension (CD) while maintaining non-aggressive mask correction where possible for mask-rule check (MRC) compliance and better yield. In this paper, we review the MB-OPC challenges, and show our integration of Proteus inverse lithography technology (ILT) with MB-OPC as the solution to these challenges.

Process window and integration results for full-chip model-based assist-feature placement at the 32 nm node and below

Model-based assist-feature (MBAF) placement has been shown to have considerable lithographic benefits vs. rule-based assist-feature (RBAF) placement for advanced technology-node requirements. For very strong off-axis illumination, MBAF-placement methods offer improved process window, especially for so-called forbidden pitch regions, and greatly simplified tuning of AF-placement parameters. Historically, however, MBAF-placement methods had difficulties with full-chip runtime, friendliness to mask manufacturing (e.g., mask rule checks or MRCs), and methods to ensure that placed AFs do not print on-wafer. Therefore, despite their known limitations, RBAF-placement methods were still the industry de facto solution through the 45 nm technology node. In this paper, we highlight recent manufacturability advances for MBAFs by a detailed comparison of MBAF and RBAF methods. The MBAF method employed uses Inverse Mask Technology (IMT) to optimize AF placement, size, shape, and software runtime, to meet the production requirements of the 28 nm technology node and below. MBAF vs. RBAF results are presented for process window performance, and MBAF vs. OPC results are presented for full-chip runtimes. The final results show that MBAF methods have process-window advantages for technology nodes below 45 nm, with runtimes that are comparable to OPC.