Yongfa Fan

Analysis of OPC optical model accuracy with detailed scanner information

Production optical proximity correction (OPC) tools employ compact optical models in order to accurately predict complicated optical lithography systems with good theoretical accuracy. Theoretical accuracy is not the same as usable prediction accuracy in a real lithographic imaging system. Real lithographic systems have deviations from ideal behavior in the process, illumination, projection and mechanical systems as well as in metrology. The deviations from the ideal are small but non-negligible. For this study we use realistic process variations and scanner values to perform a detailed study of useful OPC model accuracy vs. the variation from ideal behavior and vs. theoretical OPC accuracy. The study is performed for different 32nm lithographic processes. The results clearly show that incorporating realistic process, metrology and imaging tool signatures is significantly more important to predictive accuracy than small improvements in theoretical accuracy.

An accurate ILT-enabling full-chip mask 3D model for all-angle patterns

As the technology node keeps shrinking down to sub-28 nm, mask topography (Mask3D) effect is one of the most influential factors to draw intensive research lately. To build a successful Mask3D compact model, the runtime efficiency, accuracy and the flexibility to handle various geometry patterns are the three most important criterion to fulfill. Different approaches have been tried to resolve the difficulties in the full-chip modeling, but so far none of the existing Mask3D modeling methods have succeeded in meeting all the three criterion at the same time. It is often seen that an existing Mask3D model to succeed in one or two criteria, but fails in the rest. In this paper, we propose our innovative full chip Mask3D modeling method to successfully handle the above criterion at the same time. To our best of knowledge, it is the first ever Mask3D modeling in literature that is be able to achieve this goal. In our modeling flow, we first analyze the Mask3D effect by using rigorous simulation as the reference and generate edge-based kernels to mimic the Mask3D effect near the feature boundaries. The flexibility of handling the kernel helps us enable the support for all-angle patterns and be extendable for edge coupling effect and off-axis illumination. Our experimental results show that with only less than 30% runtime overhead compared to the conventional Mask2D model, we are able to achieve less than 0.8 nm CD RMS on the flexible feature patterns. An ILT-based OPC and simulation result is provided to validate the capability of all-angle support of our proposed model.

A simplified reaction-diffusion system of chemically amplified resist process modeling for OPC

As semiconductor manufacturing moves to 32nm and 22nm technology nodes with 193nm water immersion lithography, the demand for more accurate OPC modeling is unprecedented to accommodate the diminishing process margin. Among all the challenges, modeling the process of Chemically Amplified Resist (CAR) is a difficult and critical one to overcome. The difficulty lies in the fact that it is an extremely complex physical and chemical process. Although there are well-studied CAR process models, those are usually developed for TCAD rigorous lithography simulators, making them unsuitable for OPC simulation tasks in view of their full-chip capability at an acceptable turn-around time. In our recent endeavors, a simplified reaction-diffusion model capable of full-chip simulation was investigated for simulating the Post-Exposure-Bake (PEB) step in a CAR process. This model uses aerial image intensity and background base concentration as inputs along with a small number of parameters to account for the diffusion and quenching of acid and base in the resist film. It is appropriate for OPC models with regards to speed, accuracy and experimental tuning. Based on wafer measurement data, the parameters can be regressed to optimize model prediction accuracy. This method has been tested to model numerous CAR processes with wafer measurement data sets. Model residual of 1nm RMS and superior resist edge contour predictions have been observed. Analysis has shown that the so-obtained resist models are separable from the effects of optical system, i.e., the calibrated resist model with one illumination condition can be carried to a process with different illumination conditions. It is shown that the simplified CAR system has great potential of being applicable to full-chip OPC simulation.

Improving 3D resist profile compact modeling by exploiting 3D resist physical mechanisms

3D Resist profile aware OPC has becoming increasingly important to address hot spots generated at etch processes due to the mass occurrence of non-ideal resist profile in 28nm technology node and beyond. It is therefore critical to build compact models capable of 3D simulation for OPC applications. A straightforward and simple approach is to build individual 2D models at different image depths either based on actual wafer measurement data or virtual simulation data from rigorous lithography simulators. Individual models at interested heights can be used by downstream OPC/LRC tools to account for 3D resist profile effects. However, the relevant image depths need be predetermined due to the discontinuous nature of the methodology itself. Furthermore, the physical commonality among the individual 2D models may deviate from each other as well during the separate calibration processes. To overcome the drawbacks, efforts are made in this paper to compute the whole bulk image using Hopkins equation in one shot. The bulk image is then used to build 3D resist models. This approach also opens the feasibility of including resist interface effects (for example, top or bottom out-diffusion), which are important to resist profile formation, into a compact 3D resist model. The interface effects calculations are merged into the bulk image Hopkins equation. Simulation experiments are conducted to demonstrate that resist profile heavily rely on interface conditions. Our experimental results show that those interface effects can be accurately simulated with reference to rigorous simulation results. In modeling reality, such a 3D resist model can be calibrated with data from discrete image planes but can be used at arbitrary interpolated planes. One obvious advantage of this 3D resist model approach is that the 3D model is more physically represented by a common set of resist parameters (in contrast to the individual model approach) for 3D resist profile simulation. A full model calibration test is conducted on a virtual lithography process. It is demonstrated that 3D resist profile of the process can be precisely captured by this method. It is shown that the resist model can be carried to a different lithography process with same resist setup but a different illumination source without model any accuracy degradation. In an additional test, the model is used to demonstrate the capability of resist 3D profile correction by ILT.

Efficient full-chip mask 3D model for off-axis illumination

Mask topography (Mask3D) effect is one of the most influential factors in sub-28 nm technology node. To build a successful Mask3D compact model, the runtime efficiency, accuracy and the flexibility to handle various geometry patterns are the three most important criterion to fulfill. In the meanwhile, Mask3D modeling must be able to handle the off-axis illumination (OAI) condition accurately. In this paper, we propose our full chip Mask3D modeling method which is an extension to the edge-based Mask3D model. In our modeling flow, we first review the edge-based Mask3D model and then analyze the impact from the off-axis source. We propose a parameter-based extension to characterize the off-axis impact efficiently. We further introduce two methods to calibrate the OAI-aware parameters by using rigorous or wafer data as the reference. Our experimental results show the great calibration accuracy throughout the defocus range with OAI sources, and validate the accuracy of our two parameter calibration approach.

3D resist profile modeling for OPC applications

While critical lithographic feature size diminishes, resist profile can vary significantly as image varies. As a consequence, the final etch results are becoming more dependent on 3D resist profile rather than only a simple 2D resist image as an etch mask. Therefore, it has become necessary to build resist profile information into OPC models, which traditionally only contain 2D information in the x-y plane. At the same time, rigorous lithographic simulators are capable of modeling 3D resist profiles on a small chip area. In this work, one approach is investigated to account for 3D resist profile characteristics in full-chip OPC models with the assistance of rigorous simulation. With measurement data collected from experimental wafers, a rigorous resist model is first calibrated and verified. Then individual compact models are built to match the rigorous resist model profile at specified resist heights. The calibrated compact model for bottom resist line width corresponds to a conventional OPC model while resist profile is described by multiple models specified for certain resist heights, with each model being in the form of conventional compact models. In practice, the bottom model along with one or two models at critical heights are usually sufficient to detect sites where etch results become sensitive to resist profile. It has been found that the rigorous resist profile model can be well matched by the suggested compact models. For a quick application demonstration, hot spots of the etch results in the test case have been shown to be successfully captured by the calibrated compact models.

Resist development modeling for OPC accuracy improvement

A precise lithographic model has always been a critical component for the technique of Optical Proximity Correction (OPC) since it was introduced a decade ago [1]. As semiconductor manufacturing moves to 32nm and 22nm technology nodes with 193nm wafer immersion lithography, the demand for more accurate models is unprecedented to predict complex imaging phenomena at high numerical aperture (NA) with aggressive illumination conditions necessary for these nodes. An OPC model may comprise all the physical processing components from mask e-beam writing steps to final CDSEM measurement of the feature dimensions. In order to provide a precise model, it is desired that every component involved in the processing physics be accurately modeled using minimum metrology data. In the past years, much attention has been paid to studying mask 3-D effects, mask writing limitations, laser spectrum profile, lens pupil polarization/apodization, source shape characterization, stage vibration, and so on. However, relatively fewer studies have been devoted to modeling of the development process of resist film though it is an essential processing step that cannot be neglected. Instead, threshold models are commonly used to approximate resist development behavior. While resist models capable of simulating development path are widely used in many commercial lithography simulators, the lack of this component in current OPC modeling lies in the fact that direct adoption of those development models into OPC modeling compromises its capability of full chip simulation. In this work, we have successfully incorporated a photoresist development model into production OPC modeling software without sacrificing its full chip capability. The resist film development behavior is simulated in the model to incorporate observed complex resist phenomena such as surface inhibition, developer mass transport, HMDS poisoning, development contrast, etc. The necessary parameters are calibrated using metrology data in the same way that current model calibration is done. The method is validated with a rigorous lithography process simulation tool which is based on physical models to simulate and predict effects during the resist PEB and development process. Furthermore, an experimental lithographic process was modeled using this new methodology, showing significant improvement in modeling accuracy in compassion to a traditional model. Layout correction test has shown that the new model form is equivalent to traditional model forms in terms of correction convergence and speed.

Mask compensation for process flare in 193nm very low k1 lithography

Traditional rule-based and model-based OPC methods only simulate in a very local area (generally less than 1um) to identify and correct for systematic optical or process problems. Despite this limitation, however, these methods have been very successful for many technology generations and have been a major reason for the industry being able to tremendously push down lithographic K1. This is also enabled by overall good across-exposure field lithographic process control which has been able to minimize longer range effects across the field. Now, however, the situation has now become more complex. The lithographic single exposure resolution limit with 1.35NA tools remains about 80nm pitch but the final wafer dimensions and final wafer pitches required in advanced technologies continue to scale down. This is putting severe strain on lithographic process and OPC CD control. Therefore, formerly less important 2nd order effects are now starting to have significant CD control impact if not corrected for. In this paper, we provide examples and discussion of how optical and chemical flare related effects are becoming more problematic, especially at the boundaries of large, dense memory arrays. We then introduce a practical correction method for these systematic effects which reuses some of the recent long range effect correcting OPC techniques developed for EUV pattern correction (such as EUV flare). We next provide analysis of the benefits of these OPC methods for chemical flare issues in 193nm lithography very low K1 lithography. Finally, we summarize our work and briefly mention possible future extensions.