Yu-Min Lin

Electromigration in Ni/Sn intermetallic micro bump joint for 3D IC chip stacking

In this study, we used a chip-on-chip test vehicle with 30μm pitch lead-free solder micro bump to study the electromigration reliability of solder micro bump interconnection used for 3D chip stacking. The structure of micro bump composed of Sn2.5Ag solder material with Cu/Ni under bump metallization (UBM) was selected. Two types of interconnection were chosen to evaluate the effect of the joint structure on electromigration behavior. The type I was the chip stacking sample with the IMC / Sn (5 um thick) / IMC joint structure, while the type II was the sample with fully transformed Ni3Sn4 intermetallic (IMC) joints made by the post-treatment of long time thermal aging. Electromigration test was performed on the four point Kelvin structure and daisy-chain structure under the current stressing of 104∼105 A/cm2 at an ambient temperature of 150°C. During the electromigration test, the resistance increase was in-situ monitored to determine the definite time to failure. The microstructure evolution was also examined at different stages of joint resistance increase. From the testing results, the rapid increase of joint resistance was found at the early stage under current stressing in the type I micro bump. After that, the joint resistance increase became slower. This mild increasing stage was much longer than the early stage. For the type II sample, however, the resistance increasing rate was quiet lower than that of the type I sample at the identical testing time. With a higher current density in the order of 105 A/cm2 in the micro joint, the effect of joule heating caused the damage happened in Al trace and Cu UBM while the residual Sn solder had been transformed to be Ni3Sn4 IMC totally and few voids were found around IMC by the microstructure observation. When applied a current density in the order of 104 A/cm2 on the micro joint, the residual Sn was also fully transformed to be IMC. However, the failure mode of the micro joint is not clear yet because the experiments are still on-going. The resistance variation is showing a steady state under such a condition of current stressing and so far no open failure happened.

Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30μm pitch lead-free solder micro bumps and reliability characterization

3D IC integration can be accomplished by using the approaches such as chip-on-chip, chip-on-wafer and wafer-on-wafer integration. The scheme of chip-on-chip shows the advantages of high flexibility and yield during assembly process. However, low fabrication throughput has been a major issue. When compared to chip-on-chip integrations, wafer-on-wafer may provide the higher manufacturing throughput but its overall yield will be limited by accumulative yield. Also, good chips are forced to bond on bad chip. Therefore, the development of chip-on-wafer integration may be a better scheme for 3D chip stacking. In this study, a high-yield and fluxless chip-on-wafer bonding process with 30μm pitch lead-free solder micro bump interconnection were demonstrated and the reliability of micro joint was also evaluated. Test chip adopted in this study had more than 3000 micro bumps with a diameter of 18μm and a pitch of 30μm. Sn2.5Ag solder material was electroplated on Cu/Ni under bump metallurgy (UBM) of both the test chip and 200mm wafer. To achieve the purpose of fluxless chip-on-wafer bonding, the plasma pre-treatment was applied to both the test chips and bonded wafer. The thermo-compression bonding method with the gap control capability was also carried out. In this work, the fluxless thermo-compression bonding having more than 90% CoW yield had been accomplished. The factor of Sn thickness was found to evidently influence the CoW yield. With the optimized plasma treatment parameters and bonding conditions, a well-aligned and robust joining of micro bump without using flux could be obtained. The results of reliability test revealed that the introduction of underfill could apparently enhance the reliability performance of micro joint under mechanical evaluation. Also, the solder micro bump joint showed excellent electromigration resistance when compared to standard flip chip bump under current stress of 5×10−4 A/cm2 at an ambient temperature of 150°C.

Effects of UBM structure/material on the reliability performance of 3D chip stacking with 30μm-pitch solder micro bump interconnections

With the increased demand of functionality in electronic device, three dimensional integration circuits technology together with downscaling of interconnection pitch present an important role for the development of next generation electronics. In the current types of interconnects, solder micro bumps have received much attention due to its low cost in material and process. For fine pitch solder micro bump interconnections, selection of under bump metallurgical material is a crucial issue because the UBM structure/material will show a significant influence on the reliability performances of the solder micro bump joints. However, which UBM structure/material for fine pitch solder micro bump joint presents the better reliability properties is not concluded yet until now. In this study, the effect of UBM structural/material on the reliability properties of lead-free solder micro interconnections with a pitch of 30μm was discussed. The chip-on-chip test vehicle with solder micro bump interconnections having a diameter of 18 μm was adopted to evaluate the effects of UBM structure/material. There were more than 3000 micro bumps with Sn2.5Ag solder material on both the silicon chip and carrier. In this study, three types of UBM were selected on the silicon carrier: they were single copper layer with a thickness of 8μm; the Cu/Ni layer with the thickness of 5μm/3μm and the Cu/Ni/Au layer with the thickness of 5μm/3μm/0.5μm. The UBM was electro-plated on the Al trace and then the Sn2.5Ag solder with a thickness of 5 μm was deposited. For the silicon carrier with the bump structure of Cu/Sn and Cu/Ni/Sn, the silicon test chip with solder micro bump of Cu/Sn was used for chip bonding. The test chip having the solder micro bump of Cu/Sn and Cu//Ni/Sn was used for bonding with the silicon carrier having the Cu/Ni/Au UBM. In chip stacking process, we adopted the fluxless thermocompression process for each type of micro joints. After chip bonding process, the fine gap between bonded chips was filled by capillary type of underfill. The influence of underfill on the reliability of solder micro bump interconnects with various combinations of UBM structures were estimated also. After the assembly process, temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were performed on the chip-stacking module to assess the effect of UBM structure/material on the reliability of solder micro bump interconnections. The results of reliability test revealed that only Cu/Sn/Au/Ni/Cu micro joint could not pass the TCT and HTS of 1000 cycles. After reliability test, the Cu/Sn/Cu joints showed the evidently microstructural evolution while the Cu/Ni/Sn/Cu joints did not show apparent microstructure change among all the types of micro joints and still revealed the most contents of residual solder within the joint. On the other hand, the existence of Au layer upon the UBM caused the complicated interface reaction between solder and UBM, which presented a negative effect during long-term reliability performance. The reliability results also displayed that the introduction of underfill could apparently enhance the reliability of micro joint under mechanical evaluation. From the results of EM reliability test, all the types of the micro joints showed excellent electromigration resistance under current stress of 0.08A at an ambient temperature of 150°C irrespective of the types of UBM. This superior property was attributed to the microstructure change transformed from the solder joint to the IMC joint within the solder micro bump interconnections during electromigration test. All the results of reliability test illustrated that the selection of UBM structure/material well influenced the reliability performance of fine-pitch solder micro bump interconnections in 3D chip stacking.

Process, assembly and electromigration characteristics of glass interposer for 3D integration

Glass interposer is proposed as a superior alternative to organic and silicon-based interposers for 3DIC packaging in the near future. Because glass is an excellent dielectric material and could be fabricated with large size, it provides several attractive advantages such as excellent electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In this paper, we investigated the EM performance of Cu RDL line with glass substrate. Three different physical properties of glass materials were used for studying the EM performance of Cu RDL line. The used testing conditions are under 150~170 °C and 300~500mA. The glass type material with best performance was applied for glass interposer process integration and assembly investigation. Therefore, a wafer-level 300mm glass interposer scheme with topside RDLs, Cu TGVs, bottom side RDLs, Cu/Sn micro-bump and PBO passivation has been successfully developed and demonstrated in the study. The chip stack modules with glass interposer were assembled to evaluate their electrical characteristics. Pre-conditioning test was performed on the chip stacking module with the glass interposer to assess the reliability of the heterogeneous 3D integration scheme. All the results indicate that the glass interposer with polymer passivation can be successfully integrated with lower cost processes and assembly has been successfully developed and demonstrated in the study.

Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP

In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments.

Performance and process characteristic of glass interposer with through-glass-via(TGV)

Primary approach of 3DIC packaging usually adopts organic substrates or silicon interposer as the intermedium between multi-integrated circuits (ICs) and printed circuit board. Current organic substrates face the limitations in poor dimensional stability, trace density and CTE mismatch to silicon. Silicon interposer is a good solution for high-pin-count ICs and high performance applications based on the mature Si technology of advance via formation and fine line Cu damascene multilevel interconnection process, but silicon interposer is limited by high cost. Glass is proposed as ideal interposer material due to high resistivity, low dielectric constant, low insertion loss and adjustable coefficient of thermal expansion (CTE) for the 3DIC assembly integration and most importantly low cost solution, [1-4]. The main focus of this paper is on (a) TGV electrical design, simulation and characterization, (b) wafer level integration in TGV formation, two RDL on the front-side, one RDL on the backside and polymer-based PBO for the passivation, (c) assembly process of silicon chip stack on the glass interposer with Kelvin resistance measurement. The glass interposer was assessed to have excellent electrical characteristics and is potentially to be applied for 3D product applications.

A novel compliant-bump structure for ACA-bonded chip-on-flex (COF) interconnects with ultra-fine pitch

As the growing demand for high-density electronic applications, a novel COF package with sidewall-insulated Au-coated polyimide (PI) compliant-bumps using a double-layer ACA that can meet the assembly requirement is thus developed for ultra-fine pitch interconnects in this work.

Investigation of the process for glass interposer

Through glass via (TGV) interposer fabrication processes are critical techniques in 3D-IC integration, providing the short interconnection among different stacked chips and substrate. Nowadays, silicon is a mature material in semiconductor technology, but glass, a dielectric material, provides an attractive option due to its intrinsic characteristics for the advantages of electrical isolation, better RF performance, flexibility with CTE and most importantly low cost solution. In this investigation, the glass interposer by using TSV industry equipment and tooling was evaluated and developed and there are many challenges for processing. For process, the major differences between Glass and Si interposer are method for via formation and isolation. The test vehicle for Glass interposer is successfully processed. Glass material is composed with SiOx, it is good isolation for electrical current. The polymer-based PBO is used for passivation. For structure of glass interposer, there is one RDL on the front-side and backside, respectively. The other structure is 2 RDL on the front-side and one RDL one the backside. The CD of through glass via is 30 μm, it is formed by Corning Co. Cu overburden and Ti barrier are removed by wet etching process. For top RDL (line-width = 20μm), Cu plating process with seed layer (Ti/Cu) wet-etching process is applied. The PBO material is used for passivation, the process temperature is blow 200°C. Top UBM (15μm in diameter; 4μm/5μm-thick Cu/Sn) is formed with a top passivation opening (15μm). The structure is analyzed and demonstrated by SEM analysis. All the results indicate that the glass interposer with polymer passivation can be preceded and the cost for process is cheaper than Si interposer.

Assembly of 3D chip stack with 30μm-pitch micro interconnects using novel arrayed-particles anisotropic conductive film

As the demands of functionality and performance for electronic products increase, three-dimensional chip stacking with high-density I/O has received much attention. For high density interconnections packaging, solder micro bumps are adopted extensively. However, its process temperature is high during chip stacking process. High bonding temperature would be easy to lead chip damage and chip warpage. For diminishing the thermal damage resulted from the high bonding temperature during chip stacking, we used the anisotropic conductive film as an intermediate layer to bond the chips. In this paper, a new type of ACF with Ni/Au-coated polymer arrayed particles was adopted for assembling a chip stack module with a micro bump pitch of 30μm. The reliability of the chip stack assembled by such novel material was evaluated and estimated also. The chip-to-chip stack module having more than 3000 I/Os with a pitch of 30μm was used as the test vehicle. The structure of Cu/Ni/Au micro bump was chosen and fabricated on both the silicon chip and substrate. The silicon chip was bonded onto the silicon substrate using the arrayed-particles ACF material after ACF lamination process. The optimized lamination conditions and the effects of bonding pressure and temperature were evaluated and determined by considering the particle deformation, electrical performance and adhesive flow phenomenon. After optimizing the lamination and bonding parameters, the reliability of the assembled C2C module was evaluated by Pre-condition test, TCT and THST. Cross-sectioned inspection of micro joints by scanning electron microscopy, observation of interface between adhesive and silicon by scanning acoustic tomography, and adhesion test of ACF film after bonding and precondition were conducted to determine the failure modes of the ACF joining. After precondition test, less than 15% of daisy-chain resistance variation was found. The ACF joints with stable electrical resistance could be obtained by such kind of novel material. Also, no any obvious ACF delamination could be observed. The adhesion strength did not show any degradation after precondition test. The reliability test results revealed that the assembled C2C module by the arrayed-particles ACF showed the acceptable reliability performance in TCT and THST. The results of failure analysis displayed that the connectivity of ACF joints was damaged by induced thermal stress coming from the mismatch of CTE between adhesive matrix and conductive particles during environmental testing. This study presented that the arrayed-particles anisotropic conductive film adopted had great potential and could be applied for the 3D chip stacking assembly with fine pitch interconnects.

Development of high throughput adhesive bonding scheme by wafer-level underfill for 3D die-to-interposer stacking with 30µm-pitch micro interconnections

In 3D integration, die stacking together with underfilling by capillary-type underfill are the principal processes within whole conventional assembly process. How to integrate and shorten the total process steps during assembly and increase the die-stacking yield especially for thin die stack to improve the throughput that can meet the requirement from industry will be a crucial issue. In this investigation, we proposed the high throughput adhesive bonding scheme by using wafer-level underfill material for the die-to-interposer stacking with 30μm-pitch micro interconnections. The reliability characterization of the die-to-interposer stack by such bonding scheme was implemented and confirmed. Die-to-interposer test vehicle was adopted to develop the proposed adhesive bonding scheme. The micro joints of electroplating Cu/Sn solder micro bumps joined with electroplating Cu/Ni/Au micro bumps was selected as the joining structure. There were more than 3000 bumps designed in the test vehicle. Three types of wafer-level underfill material were evaluated and selected to be the suitable processing material. The optimized die-to-interposer boding profile by wafer-level underfill were developed and determined for the purpose of high throughput in this study. After assembly process by the developed adhesive bonding scheme, reliability characterization was conducted on the die-to-interposer modules. Pre-conditioning, temperature cycling test (TCT), thermal & humidity storage test (THST) and die shear test were selected to assess reliability performance of the die-to-interposer module assembled by the proposed adhesive bonding scheme. Under the optimized bonding profile, one-die assembly could be finished less than 20 seconds, which was comparable to the process time of thermocompression bonding only. Also, the wetting and joining abilities of the micro joints were as good as those bonded by thermocompression bonding with flux and no voids were found between dies. By such adhesive bonding scheme, processes of flux cleaning and underfill dispensing and curing were no longer necessary, which could apparently enhance the throughput of die stacking. Results of reliability tests revealed that no electrical-connectivity fail and delamination happened on those die-to-interposer modules with 30μm-pitch micro interconnects after TCT of 1000 cycles and THST of 1000 hours though die shear strength showed a slight degradation less than 20%. In this investigation, the developed high throughput adhesive bonding scheme displayed the high potential that could be suitable and applicable for fine pitch 3D integration and high volume manufacturing requirements.