Hugh Mair

90nm low leakage SoC design techniques for wireless applications

The new generation of multimedia-application processors requires a drastic leakage reduction to bring the standby current to 50/spl mu/A. An efficient set of leakage reduction techniques, including power gating, memory retention, voltage scaling, and dual V/sub t/, is employed on a 50M transistor, 80mm/sup 2/ IC, fabricated in a 90nm CMOS technology, resulting in a 40/spl times/ leakage reduction.

An architecture of high-performance frequency and phase synthesis

Frequency synthesis has many applications in todays commercial electronic and telecommunication system design. Some techniques exist which can be used to generate a frequency that is an integer or fractional multiple of a reference frequency. This architecture is used to generate a signal of any desired frequency in a certain range from multiple reference signals with same frequency but different phases. These reference signals may come from a voltage-controlled oscillator (VCO) which is close looped with a reference clock by a phase-lock loop (PLL). This architecture provides some unique features, superior quality, and ease of implementation. In some cases, the synthesized frequency is time-average frequency. The signal can be treated as a carrier signal frequency modulated by another signal. Various phase-shifted versions and duty cycle versions of this signal can also be generated from this architecture. This architecture also has direct application to spread spectrum clock generation.

A 65-nm Mobile Multimedia Applications Processor with an Adaptive Power Management Scheme to Compensate for Variations

In this paper we present the SmartReflextrade power management techniques implemented on the OMAP3430 Mobile Multimedia Applications Processor. By using multiple voltage domains, fine grain power domains, split-rail memories, and adaptive compensation, SoC active power reduction of 66% and leakage power reduction of 2~3 orders of magnitude was achieved. OMAP3430 contains more than 150M transistors.

A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques

System on Chip (SoC) integration is the theme of the first integrated 3.5G baseband and multimedia applications processor fabricated using a low-power digital and analog design platform and 45nm process technology. This SoC supports mobile standards: HSUPA/HSDPA, WCDMA, EDGE/GPRS/GSM and applications such as MPEG-4 video streaming, Java and MP3 audio. The high- performance multimedia, multiprocessor engine includes an 840MHz ARM1176, a 480MHz TMS320C55x DSP, and a 240MHz image processor.

A 28 nm 0.6 V Low Power DSP for Mobile Applications

Processors for next generation mobile devices will need to operate across a wide supply voltage range in order to support both high performance and high power efficiency modes of operation. However, the effects of local transistor threshold (VT) variation, already a significant issue in todays advanced process technologies, and further exacerbated at low voltages, complicate the task of designing reliable, manufacturable systems for ultra-low voltage operation. In this paper, we describe a 4-issue VLIW DSP system-on-chip (SoC), which operates at voltages from 1.0 V down to 0.6 V. The SoC was implemented in 28 nm CMOS, using a cell library and SRAMs optimized for both high-speed and low-voltage operating points. A new statistical static timing analysis (SSTA) methodology was also used on this design, in order to more accurately model the effects of local VT variation and achieve a reliable design with minimal pessimism.

SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors

In the last couple of decades, handheld wireless devices such as cell phones have become one of the most prolific electronic devices in history. With this has come an exploding demand for performance and features that cover almost every aspect of our digital multimedia interconnected lives including 3-D gaming, still and video cameras, WAN, Bluetooth, high-speed data connections, and so on. As ever increasing features continue to be integrated into these products, there is an ongoing need to develop innovative ways to reduce power consumption and extend battery life. Only through continual process and circuit cooptimization are we able to reap the benefits of technology scaling required to meet the feature and performance demands in the face of increasing process variations and exponentially increasing leakage currents. As a result, SmartReflex power and performance technologies have been developed and applied to 90 nm, 65 nm, and 45 nm system-on-chip (SoC), to achieve optimal power and performance. SmartReflex technologies consist of two major components to optimize SoC power and performance: static and dynamic techniques. Static techniques like power-gating, retention and off-mode are used to lower leakage and allow for extended battery lifetimes for standby times. Dynamic techniques such as dynamic power switching, adaptive voltage scaling, dynamic voltage/frequency scaling with split-rail memories, and adaptive body-biasing address active power and performance challenges. These techniques enable SoC solutions with the performance of the latest process technology and provide the user with advanced multimedia features with orders of magnitude of power reduction.

Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2V pp voltage-mode driver

In networking systems today data rates are increasing beyond 15Gb/s and yet the installed backplanes are made of low cost materials with losses in excess of 30dB at 7.5GHz. Standards, such as IEEE802.3ap-10GBASE-KR and OIF-CEI25G, are specifying SerDes requirements for channels with 25dB loss at Nyquist and this has driven the development of SerDes with 4 or 5 tap DFEs [1]. Until now, solutions for 34dB or more channel loss have been limited to 10.3Gb/s or below [2,3], whereas this paper describes an adaptive 14-tap DFE that achieves a 10−17 BER across a 34dB loss channel at 16Gb/s for a power of 235mW/lane. A baud-rate CDR technique is specifically developed that gives excellent locking characteristics and alignment for use with a speculative DFE together with an enhanced swing TX voltage mode driver.

A design platform for 90-nm leakage reduction techniques

Methodology, EDA flow, scripts, and documentation play a tremendous role in the deployment and standardization of advanced design techniques. In this paper we focus not only on leakage reduction techniques but also on their deployment as a worldwide infrastructure as the added-value resides not only in the techniques themselves but also in the way they are implemented to build an efficient, re-usable, robust, low cost and portable platform. Techniques have been silicon proven on the 90-nm TI CMOS technology and is commonly used to design SoC with complexities over 100 million transistors.

Re-Using Clock Management Unit to implement Power Gating and Retention for Leakage Reduction at the 65-nm Technology Node

Leakage power management, wireless SoC In this paper we present a leakage management system which takes advantage of the existing clock gating infrastructure. This methodology avoids both RTL and software changes, at the block and chip level. We illustrate this approach with a 65-nm digital base band modem while achieving standby leakage in the 100-uA range and overall 1200X leakage reduction including process, circuit and system optimization.

Solutions for logic and processor core design at the 45nm technology node & and below

In this paper we present an overview of techniques and methodologies for processor cores and digital SoC integration showing how process sensors, circuitry and system control cooperate in order to achieve the best power, performance, area and yield trade-off. We cover combinatorial and sequential logic as well as memory cores in the context of retention, power gating and adaptive features. Various techniques are also given as example and illustrated by silicon measurements.