Sapumal Wijeratne

A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit

This paper describes a fourth generation Intel Pentium 4 processor integer execution core operating at 9 GHz in a 1.3-V, 65-nm CMOS technology at 70degC. Low-voltage-swing circuits of the 90-nm design are replaced by: 1) 2times frequency fast clock (FCLK)-optimized domino clocking scheme; 2) segmented arithmetic and logic unit (ALU) front-end multiplexer; 3) sparse-tree ALU adder; 4) merged add/subtract sparse-tree address generation unit (AGU) design; 5) speculative RC-delay-optimized rotator; and 6) single-rail L0 cache and alignment multiplexer, resulting in 8.4% reduction in integer core normalized active power and 42% reduction in normalized leakage power. The use of standard domino/static tools and methodologies lowers design complexity, reducing development cost and time. The redesign also reduces integer core thermal density, resulting in an 8degC reduction in CPU operating temperature

Low-voltage swing logic circuits for a Pentium/spl reg/ 4 processor integer core

The Pentium/spl reg/ 4 processor architecture uses a 2/spl times/ frequency core clock to implement low latency integer operations. Low-voltage-swing (LVS) logic circuits implemented in 90-nm technology meet the frequency demands of a third-generation integer-core design.

Low-voltage-swing logic circuits for a 7GHz x86 integer core

Pentium/spl reg/4 processor architecture uses a 2x core clock to implement low latency integer operations. Low-voltage-swing logic circuits in 90nm technology meet the frequency demands of a 3rd generation integer core, with operation demonstrated for frequencies in excess of 7GHz.

Low voltage swing logic circuits for a Pentium 4 processor integer core

The Pentium/spl reg/ 4 processor architecture uses a 2/spl times/ frequency core clock to implement low latency integer operations. Low-voltage-swing (LVS) logic circuits implemented in 90-nm technology meet the frequency demands of a third-generation integer-core design.