George L. Geannopoulos

Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process

Thermal management (TM) allows the system architect to design a cooling solution based on real-life power consumption, not peak power. The on-die thermal sensor circuit, as the core of the TM system, monitors the on-die junction temperature (Tj). We present a novel high-linearity thermal sensor topology with built-in circuit support for correction of systematic shifts in the transfer function correction. Results obtained on the 65 nm Pentiumreg4 processor demonstrate the feasibility and effectiveness of the design.

Low-voltage swing logic circuits for a Pentium/spl reg/ 4 processor integer core

The Pentium/spl reg/ 4 processor architecture uses a 2/spl times/ frequency core clock to implement low latency integer operations. Low-voltage-swing (LVS) logic circuits implemented in 90-nm technology meet the frequency demands of a third-generation integer-core design.

Low-voltage-swing logic circuits for a 7GHz x86 integer core

Pentium/spl reg/4 processor architecture uses a 2x core clock to implement low latency integer operations. Low-voltage-swing logic circuits in 90nm technology meet the frequency demands of a 3rd generation integer core, with operation demonstrated for frequencies in excess of 7GHz.

Low voltage swing logic circuits for a Pentium 4 processor integer core

The Pentium/spl reg/ 4 processor architecture uses a 2/spl times/ frequency core clock to implement low latency integer operations. Low-voltage-swing (LVS) logic circuits implemented in 90-nm technology meet the frequency demands of a third-generation integer-core design.

Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor

Traditional inaccuracies during manufacturing test of the thermal sensor circuit require excessive guard-bands. These guard-bands increase the chance of unnecessary microprocessor throttling and could introduce a less-than optimum power and thermal design envelope. Circuit techniques that minimize these errors are discussed, including an improved temperature-independent voltage pump, a remote thermal sensing scheme for hot-spot to sensor offset reduction, and a self-heating error calibration method. Experimental data obtained on a high performance 65nm Intel® Pentium® 4 microprocessor demonstrates the feasibility and effectiveness of these techniques, providing a combined potential accuracy improvement of up to 17°C.

A high performance 0.35-/spl mu/m 3.3-V BiCMOS technology optimized for product porting from a 0.6-/spl mu/m 3.3-V BiCMOS technology

A 0.35-/spl mu/m logic technology has been developed with high performance transistors and four layers of planarized metal interconnect. A 2.5-V version offers lower power and higher performance. A 3.3-V BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6-/spl mu/m 3.3-V BiCMOS process. A two-step design process for converting an existing production worthy 0.6-/spl mu/m 3.3-V BiCMOS design to a 0.35-/spl mu/m design is described. The silicon results are described.