David Richard Esler

Voids in thermal interface material layers and their effect on thermal performance

One of the key challenges in the thermal management of microelectronic devices is interfaces such as those between the chip and heat spreader and between the heat spreader and heat sink or cold plate. Typically, thermal interfaces are filled with materials such as thermal adhesives and greases. Interface materials reduce the contact resistance between the mating heat generating and heat sinking units by filling voids and grooves created by the nonsmooth surface topography of the mating surfaces, thus improving surface contact and the conduction of heat across the interface. With shrinking thermal budgets, the role of these layers in the cooling of microelectronic devices has become more critical. Voids in thermal interface material (TIM) layers may be trapped during the flow of the TIM during assembly, due to outgassing during the curing process, or due to insufficient volume. The negative effect of such voids on the thermal resistance of a TIM layer can be devastating. In applications where the TIM performs the function of a structural adhesive, voids may negatively affect the adhesion strength and reliability of the TIM layer. In this work, the effect of voids and their characteristics on the thermal performance of thermal interface adhesive layers is reported.

Micron and Submicron-Scale Characterization of Interfaces in Thermal Interface Material Systems

One of the key challenges in the thermal management of electronic packages are interfaces, such as those between the chip and heat spreader and the interface between a heat spreader and heat sink or cold plate. Typically, thermal interfaces are filled with mate-rials such as thermal adhesives and greases. Interface materials reduce the contact resistance between the mating heat generating and heat sinking units by filling voids and grooves created by the nonsmooth surface topography of the mating surfaces, thus improving surface contact and the conduction of heat across the interface. However, micron and submicron voids and delaminations still exist at the interface between the interface material and the surfaces of the heat spreader and semiconductor device. In addition, a thermal interface material (TIM) may form a filler-depleted and resin-rich region at the interfaces. These defects, though at a small length scale, can significantly deteriorate the heat dissipation ability of a system consisting of a TIM between a heat generating surface and a heat dissipating surface. The characterization of a freestanding sample of TIM does not provide a complete understanding of its heat transfer, mechanical, and interfacial behavior. However, system-level characterization of a TIM system, which includes its freestanding behavior and its interfacial behavior, provides a more accurate understanding. While, measurement of system-level thermal resistance provides an accurate representation of the system performance of a TIM, it does not provide information regarding the physical behavior of the TIM at the interfaces. This knowledge is valuable in engineering interface materials and in developing assembly process parameters for enhanced system-level thermal performance. Characterization of an interface material between a silicon device and a metal heat spreader can be accomplished via several techniques. In this research, high-magnification radiography with computed tomography, acoustic microscopy, and scanning electron microscopy were used to characterize various TIM systems. The results of these characterization studies are presented in this paper. System-level thermal performance results are compared to physical characterization results.

Design of a high reliability and low thermal resistance interface material for microelectronics

Thermal interface materials (TIMs) play a key role in the thermal management of microelectronic devices by providing a path of low thermal impedance between heat generating devices and heat dissipating components (heat spreader/sink). In addition, TIMs often provide mechanical coupling between the silicon device and the heat spreader/sink. During device operation, the adhesive joint between the heat generating device and heat spreader/sink is subjected to thermomechanical stresses due to differences in thermal expansion coefficients of the silicon device and the heat spreader material. The adhesive joint can consequently delaminate or debond from the mating surfaces causing a significant increase in thermal impedance across the thermal interface material. Hence, a TIM needs to offer improved thermal performance as well as enhanced reliability. In addition to these characteristics, several other requirements such as adhesion strength, response to different assembly parameters, and volatile content need to be considered and addressed during the development of a TIM. This paper discusses the development of such an interface material and a comprehensive performance evaluation of the new TIM.

Utilization of carbon fibers in thermal management of microelectronics

Power dissipation is expected to increase exponentially to 150-250 W per chip over the next decade. To manage this large heat output, it is necessary to minimize the thermal resistance between the chip and a heat dissipation unit that the device is attached to. It is therefore important to further improve the thermal performance of thermal interface materials (TIMs), which can be achieved through 1) improvement of the bulk thermal conductivity of TIMs; and/or 2) reduction of interfacial thermal resistances between the TIM and the device and/or TIM and the heat dissipation unit. The latter improvement may be obtained by enhanced physical properties of TIMs (e.g., viscosity or wetting ability) and/or surface modification of the heat dissipation unit or the inactive side of the device. Researchers have tried to take advantage of the high 1D thermal conductivities of graphite fibers, and more recently of carbon nanotubes (CNT), to reduce the thermal resistance between the chip and the heat dissipation unit. The efforts can be classified into three categories: 1) Forming pre-aligned graphite fiber or CNT films that have high bulk thermal conductivities in the heat transport direction, and applying such films as TIMs; 2) incorporating randomly oriented graphite fibers or CNT into silicone or epoxy matrices in the presence or absence of a second filler to improve bulk thermal conductivities, and applying the thus-formed blend as thermal greases, or adhesives or gels; and 3) growing CNT or graphite fibers from the heat sink/spreader surface and/or silicon backside and assembling them together with a TIM a to increase the bulk heat transport property and reduce the interfacial resistances, In this paper, we will present results for each of the three approaches, and discuss the challenges facing each one.

Readiness of SiC MOSFETs for Aerospace and Industrial Applications

This paper highlights ongoing efforts to validate performance, reliability and robustness of GE SiC MOSFETs for Aerospace and Industrial applications. After summarizing ruggedness and reliability testing performed on 1.2kV MOSFETs, two application examples are highlighted. The first demonstrates the 1.2kV device performance in a prototype high frequency 75kW Aviation motor drive. The second highlights the experimental demonstration of a 99% efficient 1.0MW solar inverter using 1.7kV MOSFET modules in a two-level topology switching at 8kHz. Both applications illustrate that SiC advantage is not only in improved performance, but also in significant system cost savings through simplifications in topology, controls, cooling and filtering.

Assembly and reliability of flip chips with a nano-filled wafer level underfill

The assembly and packaging of electronic devices today is becoming increasingly challenging and demanding because of requirements for smaller, faster and lighter products that provide increasing functionality at low cost. These requirements continue to place greater demands on the electronics industry and mandate improved packaging technology. In part, flip chip packaging technology is the response to these demands and provides a solution to these challenges. While flip chip packaging provides a solution to evolving device requirements, underfill materials are required to improve flip chip device reliability. These resins overcome poor device reliability issues resulting from the mismatch of coefficient of thermal expansion (CTE) between the silicon die and the organic substrate. However, offsetting the gains in device reliability are additional processing steps that adversely affect manufacturing productivity. To compensate for this adverse effect on manufacturing productivity, several new processes, such as wafer level underfill, have been developed. In this paper, we describe the assembly and reliability of flip chips with a nanofilled wafer level underfill (WLU). This approach allows application of the underfill material on the entire wafer, such that many chips can be underfilled simultaneously. Assembly is then carried out with a compatible epoxy flux material. Air-to-air thermal shock (AATS) results and failure mechanisms are described for this novel approach

High Performance 1.2kV-2.5kV 4H-SiC MOSFETs with Excellent Process Capability and Robustness

In this paper, we show state of the art, low on-resistance, 25mW/1.2kV and 43mW/2.5kV SiC MOSFETs with excellent design robustness and process control such that the parametric spread of key device characteristics are approaching Si products. The impact of starting material variability on device performance is shown and design sensitivity curves are presented.

Development of a novel filled no-flow underfill material for flip chip applications

Flip chip package design has a significant drawback related to the mismatch of coefficient of thermal expansion (CTE) between the silicon die and the organic substrate. This CTE mismatch creates stress on the solder joints during thermal excursions, which reduces the fatigue lifetime of the solder joints. This leads to premature failures of the package. However, package reliability can be improved by the application of an underfill material. In this communication, we report the development of a novel filled no-flow underfill material utilizing proprietary filler technology, which provides a previously unobtainable balance of low CTE, high glass transition temperature (Tg), and good solder joint formation. The fluxing parameters and effect of catalyst level on assembly yield are presented. Assembly results (yield, void area) are presented and compared with commercially available no-flow underfill materials.

SiC MOSFET design considerations for reliable high voltage operation

SiC MOSFETs have demonstrated continued performance improvement and maturation in the areas of Gate oxide stability and reliability over the past years. While necessary, this alone is not sufficient to achieve reliable high voltage operation. In this paper, the design constraints impacting high voltage reliability and their impact on SiC MOSFET performance at useful operating conditions are discussed. Experimental results are demonstrated with industry benchmark, reliable operation of up to Tj=200°C with 1.2kV/25mOhm SiC MOSFETs and Tj=175°C, 1.7kV/450A all-SiC MOSFET Dual-Switch modules. Avalanche ruggedness of the high-performance devices is also demonstrated with single-pulse energy densities of 9–15J/cm2 recorded with Drain currents as high as ID= 90A for 0.2cm2 die.

Thermal Resistance of Bond-Lines Formed With Composite Thermal Interface Materials

Measurements and modeling of the thermal resistance of thin (< 100 microns) bond-lines are reported for composite thermal interface materials (TIMs). The composite TIMs consist of alumina particles dispersed in a polymer matrix to form six different adhesive materials. These model TIMs have a common matrix material and are distinguished by their particle size distributions. Bond-lines are formed in a three-layer assembly consisting of a substrate-TIM-substrate structure. The thermal resistance of the bond-line is measured, as a function of bond-line thickness, using the laser flash-technique. A linear variation of resistance with bond-line thickness is observed; Rbl = β · Lbl + Ro . A model is presented that predicts the effective thermal conductivity of the composite as a function of the particle and matrix conductivity, the particle-matrix surface conductance, the particle volume fraction and the particle size distribution. Specifically a method is introduced to account for a broad, continuous size distribution. A particle-matrix surface conductance value of ∼10W/mm2 K is found to give good agreement between the measured and predicted effective thermal conductivity values of the composite TIMs.Copyright